key_buffer.tan.rpt

电子闹钟：基于fpga的电子闹钟设计

+-----------------------------------------------------------------------------+
; tco                                                                         ;
+-------+--------------+------------+-----------+----------------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To             ; From Clock ;
+-------+--------------+------------+-----------+----------------+------------+
; N/A   ; None         ; 6.626 ns   ; n_t[0][0] ; new_time[0][0] ; clk        ;
; N/A   ; None         ; 6.609 ns   ; n_t[3][0] ; new_time[3][0] ; clk        ;
; N/A   ; None         ; 6.570 ns   ; n_t[0][1] ; new_time[0][1] ; clk        ;
; N/A   ; None         ; 6.549 ns   ; n_t[2][1] ; new_time[2][1] ; clk        ;
; N/A   ; None         ; 6.395 ns   ; n_t[2][2] ; new_time[2][2] ; clk        ;
; N/A   ; None         ; 6.368 ns   ; n_t[1][0] ; new_time[1][0] ; clk        ;
; N/A   ; None         ; 6.367 ns   ; n_t[2][0] ; new_time[2][0] ; clk        ;
; N/A   ; None         ; 6.351 ns   ; n_t[1][1] ; new_time[1][1] ; clk        ;
; N/A   ; None         ; 6.342 ns   ; n_t[3][1] ; new_time[3][1] ; clk        ;
; N/A   ; None         ; 6.236 ns   ; n_t[1][2] ; new_time[1][2] ; clk        ;
; N/A   ; None         ; 6.234 ns   ; n_t[0][2] ; new_time[0][2] ; clk        ;
; N/A   ; None         ; 6.217 ns   ; n_t[3][3] ; new_time[3][3] ; clk        ;
; N/A   ; None         ; 6.102 ns   ; n_t[0][3] ; new_time[0][3] ; clk        ;
; N/A   ; None         ; 6.099 ns   ; n_t[2][3] ; new_time[2][3] ; clk        ;
; N/A   ; None         ; 6.071 ns   ; n_t[1][3] ; new_time[1][3] ; clk        ;
; N/A   ; None         ; 6.050 ns   ; n_t[3][2] ; new_time[3][2] ; clk        ;
+-------+--------------+------------+-----------+----------------+------------+


+-------------------------------------------------------------------------+
; th                                                                      ;
+---------------+-------------+-----------+--------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To        ; To Clock ;
+---------------+-------------+-----------+--------+-----------+----------+
; N/A           ; None        ; 1.124 ns  ; key[0] ; n_t[0][0] ; clk      ;
; N/A           ; None        ; 0.502 ns  ; key[1] ; n_t[0][1] ; clk      ;
; N/A           ; None        ; -2.588 ns ; key[3] ; n_t[0][3] ; clk      ;
; N/A           ; None        ; -2.597 ns ; key[2] ; n_t[0][2] ; clk      ;
+---------------+-------------+-----------+--------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Oct 05 10:02:18 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off key_buffer -c key_buffer --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "n_t[1][2]" and destination register "n_t[2][2]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.544 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y34_N3; Fanout = 2; REG Node = 'n_t[1][2]'
            Info: 2: + IC(0.311 ns) + CELL(0.149 ns) = 0.460 ns; Loc. = LCCOMB_X64_Y34_N22; Fanout = 1; COMB Node = 'n_t[2][2]~feeder'
            Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.544 ns; Loc. = LCFF_X64_Y34_N23; Fanout = 2; REG Node = 'n_t[2][2]'
            Info: Total cell delay = 0.233 ns ( 42.83 % )
            Info: Total interconnect delay = 0.311 ns ( 57.17 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.690 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y34_N23; Fanout = 2; REG Node = 'n_t[2][2]'
                Info: Total cell delay = 1.536 ns ( 57.10 % )
                Info: Total interconnect delay = 1.154 ns ( 42.90 % )
            Info: - Longest clock path from clock "clk" to source register is 2.690 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y34_N3; Fanout = 2; REG Node = 'n_t[1][2]'
                Info: Total cell delay = 1.536 ns ( 57.10 % )
                Info: Total interconnect delay = 1.154 ns ( 42.90 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "n_t[0][2]" (data pin = "key[2]", clock pin = "clk") is 2.827 ns
    Info: + Longest pin to register delay is 5.553 ns
        Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_D23; Fanout = 1; PIN Node = 'key[2]'
        Info: 2: + IC(4.468 ns) + CELL(0.149 ns) = 5.469 ns; Loc. = LCCOMB_X64_Y34_N0; Fanout = 1; COMB Node = 'n_t[0][2]~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 5.553 ns; Loc. = LCFF_X64_Y34_N1; Fanout = 2; REG Node = 'n_t[0][2]'
        Info: Total cell delay = 1.085 ns ( 19.54 % )
        Info: Total interconnect delay = 4.468 ns ( 80.46 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.690 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y34_N1; Fanout = 2; REG Node = 'n_t[0][2]'
        Info: Total cell delay = 1.536 ns ( 57.10 % )
        Info: Total interconnect delay = 1.154 ns ( 42.90 % )
Info: tco from clock "clk" to destination pin "new_time[0][0]" through register "n_t[0][0]" is 6.626 ns
    Info: + Longest clock path from clock "clk" to source register is 2.698 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X30_Y35_N11; Fanout = 2; REG Node = 'n_t[0][0]'
        Info: Total cell delay = 1.536 ns ( 56.93 % )
        Info: Total interconnect delay = 1.162 ns ( 43.07 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.678 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y35_N11; Fanout = 2; REG Node = 'n_t[0][0]'
        Info: 2: + IC(0.850 ns) + CELL(2.828 ns) = 3.678 ns; Loc. = PIN_J10; Fanout = 0; PIN Node = 'new_time[0][0]'
        Info: Total cell delay = 2.828 ns ( 76.89 % )
        Info: Total interconnect delay = 0.850 ns ( 23.11 % )
Info: th for register "n_t[0][0]" (data pin = "key[0]", clock pin = "clk") is 1.124 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.698 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X30_Y35_N11; Fanout = 2; REG Node = 'n_t[0][0]'
        Info: Total cell delay = 1.536 ns ( 56.93 % )
        Info: Total interconnect delay = 1.162 ns ( 43.07 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 1.840 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; PIN Node = 'key[0]'
        Info: 2: + IC(0.628 ns) + CELL(0.149 ns) = 1.756 ns; Loc. = LCCOMB_X30_Y35_N10; Fanout = 1; COMB Node = 'n_t[0][0]~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 1.840 ns; Loc. = LCFF_X30_Y35_N11; Fanout = 2; REG Node = 'n_t[0][0]'
        Info: Total cell delay = 1.212 ns ( 65.87 % )
        Info: Total interconnect delay = 0.628 ns ( 34.13 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Oct 05 10:02:19 2008
    Info: Elapsed time: 00:00:02