📄 key_buffer.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register n_t\[1\]\[2\] n_t\[2\]\[2\] 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"n_t\[1\]\[2\]\" and destination register \"n_t\[2\]\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.544 ns + Longest register register " "Info: + Longest register to register delay is 0.544 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns n_t\[1\]\[2\] 1 REG LCFF_X64_Y34_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y34_N3; Fanout = 2; REG Node = 'n_t\[1\]\[2\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { n_t[1][2] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.311 ns) + CELL(0.149 ns) 0.460 ns n_t\[2\]\[2\]~feeder 2 COMB LCCOMB_X64_Y34_N22 1 " "Info: 2: + IC(0.311 ns) + CELL(0.149 ns) = 0.460 ns; Loc. = LCCOMB_X64_Y34_N22; Fanout = 1; COMB Node = 'n_t\[2\]\[2\]~feeder'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.460 ns" { n_t[1][2] n_t[2][2]~feeder } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.544 ns n_t\[2\]\[2\] 3 REG LCFF_X64_Y34_N23 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.544 ns; Loc. = LCFF_X64_Y34_N23; Fanout = 2; REG Node = 'n_t\[2\]\[2\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { n_t[2][2]~feeder n_t[2][2] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.233 ns ( 42.83 % ) " "Info: Total cell delay = 0.233 ns ( 42.83 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.311 ns ( 57.17 % ) " "Info: Total interconnect delay = 0.311 ns ( 57.17 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.544 ns" { n_t[1][2] n_t[2][2]~feeder n_t[2][2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.544 ns" { n_t[1][2] n_t[2][2]~feeder n_t[2][2] } { 0.000ns 0.311ns 0.000ns } { 0.000ns 0.149ns 0.084ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.690 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.690 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 2.690 ns n_t\[2\]\[2\] 3 REG LCFF_X64_Y34_N23 2 " "Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y34_N23; Fanout = 2; REG Node = 'n_t\[2\]\[2\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.573 ns" { clk~clkctrl n_t[2][2] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.10 % ) " "Info: Total cell delay = 1.536 ns ( 57.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.154 ns ( 42.90 % ) " "Info: Total interconnect delay = 1.154 ns ( 42.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl n_t[2][2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl n_t[2][2] } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.690 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.690 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 2.690 ns n_t\[1\]\[2\] 3 REG LCFF_X64_Y34_N3 2 " "Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y34_N3; Fanout = 2; REG Node = 'n_t\[1\]\[2\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.573 ns" { clk~clkctrl n_t[1][2] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.10 % ) " "Info: Total cell delay = 1.536 ns ( 57.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.154 ns ( 42.90 % ) " "Info: Total interconnect delay = 1.154 ns ( 42.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl n_t[1][2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl n_t[1][2] } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl n_t[2][2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl n_t[2][2] } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl n_t[1][2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl n_t[1][2] } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.544 ns" { n_t[1][2] n_t[2][2]~feeder n_t[2][2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.544 ns" { n_t[1][2] n_t[2][2]~feeder n_t[2][2] } { 0.000ns 0.311ns 0.000ns } { 0.000ns 0.149ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl n_t[2][2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl n_t[2][2] } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl n_t[1][2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl n_t[1][2] } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { n_t[2][2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { n_t[2][2] } { } { } } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "n_t\[0\]\[2\] key\[2\] clk 2.827 ns register " "Info: tsu for register \"n_t\[0\]\[2\]\" (data pin = \"key\[2\]\", clock pin = \"clk\") is 2.827 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.553 ns + Longest pin register " "Info: + Longest pin to register delay is 5.553 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns key\[2\] 1 PIN PIN_D23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_D23; Fanout = 1; PIN Node = 'key\[2\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key[2] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.468 ns) + CELL(0.149 ns) 5.469 ns n_t\[0\]\[2\]~feeder 2 COMB LCCOMB_X64_Y34_N0 1 " "Info: 2: + IC(4.468 ns) + CELL(0.149 ns) = 5.469 ns; Loc. = LCCOMB_X64_Y34_N0; Fanout = 1; COMB Node = 'n_t\[0\]\[2\]~feeder'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.617 ns" { key[2] n_t[0][2]~feeder } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 5.553 ns n_t\[0\]\[2\] 3 REG LCFF_X64_Y34_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 5.553 ns; Loc. = LCFF_X64_Y34_N1; Fanout = 2; REG Node = 'n_t\[0\]\[2\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { n_t[0][2]~feeder n_t[0][2] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.085 ns ( 19.54 % ) " "Info: Total cell delay = 1.085 ns ( 19.54 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.468 ns ( 80.46 % ) " "Info: Total interconnect delay = 4.468 ns ( 80.46 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.553 ns" { key[2] n_t[0][2]~feeder n_t[0][2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.553 ns" { key[2] key[2]~combout n_t[0][2]~feeder n_t[0][2] } { 0.000ns 0.000ns 4.468ns 0.000ns } { 0.000ns 0.852ns 0.149ns 0.084ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.690 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.690 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 2.690 ns n_t\[0\]\[2\] 3 REG LCFF_X64_Y34_N1 2 " "Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y34_N1; Fanout = 2; REG Node = 'n_t\[0\]\[2\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.573 ns" { clk~clkctrl n_t[0][2] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.10 % ) " "Info: Total cell delay = 1.536 ns ( 57.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.154 ns ( 42.90 % ) " "Info: Total interconnect delay = 1.154 ns ( 42.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl n_t[0][2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl n_t[0][2] } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.553 ns" { key[2] n_t[0][2]~feeder n_t[0][2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.553 ns" { key[2] key[2]~combout n_t[0][2]~feeder n_t[0][2] } { 0.000ns 0.000ns 4.468ns 0.000ns } { 0.000ns 0.852ns 0.149ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl n_t[0][2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl n_t[0][2] } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk new_time\[0\]\[0\] n_t\[0\]\[0\] 6.626 ns register " "Info: tco from clock \"clk\" to destination pin \"new_time\[0\]\[0\]\" through register \"n_t\[0\]\[0\]\" is 6.626 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.698 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.537 ns) 2.698 ns n_t\[0\]\[0\] 3 REG LCFF_X30_Y35_N11 2 " "Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X30_Y35_N11; Fanout = 2; REG Node = 'n_t\[0\]\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.581 ns" { clk~clkctrl n_t[0][0] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.93 % ) " "Info: Total cell delay = 1.536 ns ( 56.93 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 43.07 % ) " "Info: Total interconnect delay = 1.162 ns ( 43.07 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl n_t[0][0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl n_t[0][0] } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.678 ns + Longest register pin " "Info: + Longest register to pin delay is 3.678 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns n_t\[0\]\[0\] 1 REG LCFF_X30_Y35_N11 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y35_N11; Fanout = 2; REG Node = 'n_t\[0\]\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { n_t[0][0] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.850 ns) + CELL(2.828 ns) 3.678 ns new_time\[0\]\[0\] 2 PIN PIN_J10 0 " "Info: 2: + IC(0.850 ns) + CELL(2.828 ns) = 3.678 ns; Loc. = PIN_J10; Fanout = 0; PIN Node = 'new_time\[0\]\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.678 ns" { n_t[0][0] new_time[0][0] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.828 ns ( 76.89 % ) " "Info: Total cell delay = 2.828 ns ( 76.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.850 ns ( 23.11 % ) " "Info: Total interconnect delay = 0.850 ns ( 23.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.678 ns" { n_t[0][0] new_time[0][0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.678 ns" { n_t[0][0] new_time[0][0] } { 0.000ns 0.850ns } { 0.000ns 2.828ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl n_t[0][0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl n_t[0][0] } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.678 ns" { n_t[0][0] new_time[0][0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.678 ns" { n_t[0][0] new_time[0][0] } { 0.000ns 0.850ns } { 0.000ns 2.828ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "n_t\[0\]\[0\] key\[0\] clk 1.124 ns register " "Info: th for register \"n_t\[0\]\[0\]\" (data pin = \"key\[0\]\", clock pin = \"clk\") is 1.124 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.698 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.537 ns) 2.698 ns n_t\[0\]\[0\] 3 REG LCFF_X30_Y35_N11 2 " "Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X30_Y35_N11; Fanout = 2; REG Node = 'n_t\[0\]\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.581 ns" { clk~clkctrl n_t[0][0] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.93 % ) " "Info: Total cell delay = 1.536 ns ( 56.93 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 43.07 % ) " "Info: Total interconnect delay = 1.162 ns ( 43.07 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl n_t[0][0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl n_t[0][0] } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" { } { { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.840 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.840 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns key\[0\] 1 PIN PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; PIN Node = 'key\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key[0] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.628 ns) + CELL(0.149 ns) 1.756 ns n_t\[0\]\[0\]~feeder 2 COMB LCCOMB_X30_Y35_N10 1 " "Info: 2: + IC(0.628 ns) + CELL(0.149 ns) = 1.756 ns; Loc. = LCCOMB_X30_Y35_N10; Fanout = 1; COMB Node = 'n_t\[0\]\[0\]~feeder'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.777 ns" { key[0] n_t[0][0]~feeder } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.840 ns n_t\[0\]\[0\] 3 REG LCFF_X30_Y35_N11 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 1.840 ns; Loc. = LCFF_X30_Y35_N11; Fanout = 2; REG Node = 'n_t\[0\]\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { n_t[0][0]~feeder n_t[0][0] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.212 ns ( 65.87 % ) " "Info: Total cell delay = 1.212 ns ( 65.87 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.628 ns ( 34.13 % ) " "Info: Total interconnect delay = 0.628 ns ( 34.13 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.840 ns" { key[0] n_t[0][0]~feeder n_t[0][0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.840 ns" { key[0] key[0]~combout n_t[0][0]~feeder n_t[0][0] } { 0.000ns 0.000ns 0.628ns 0.000ns } { 0.000ns 0.979ns 0.149ns 0.084ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl n_t[0][0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl n_t[0][0] } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.840 ns" { key[0] n_t[0][0]~feeder n_t[0][0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.840 ns" { key[0] key[0]~combout n_t[0][0]~feeder n_t[0][0] } { 0.000ns 0.000ns 0.628ns 0.000ns } { 0.000ns 0.979ns 0.149ns 0.084ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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