key_buffer.vhd

来自「电子闹钟：基于fpga的电子闹钟设计」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
entity key_buffer is
port( key : in t_digital;
      clk : in std_logic;
      reset : in std_logic;
      new_time : out t_clock_time);
end entity;
architecture behav of key_buffer is
signal n_t : t_clock_time;
begin
  shift: process(reset,clk) is
  begin
    if reset='1' then
      n_t<=(0,0,0,0);
    elsif  (clk'event and clk='1') then
      for i in 3 downto 1 loop
        n_t(i)<=n_t(i-1);
      end loop;
      n_t(0)<=key;
   else 
      null;
    end if;
  end process shift;
  new_time<=n_t;
end behav;