alarm_counter.tan.qmsg

电子闹钟：基于fpga的电子闹钟设计

{ "Info" "ITDB_TH_RESULT" "i_current_time\[0\]\[0\]~490 new_current_time\[0\]\[0\] load_new_C -0.201 ns register " "Info: th for register \"i_current_time\[0\]\[0\]~490\" (data pin = \"new_current_time\[0\]\[0\]\", clock pin = \"load_new_C\") is -0.201 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "load_new_C destination 2.629 ns + Longest register " "Info: + Longest clock path from clock \"load_new_C\" to destination register is 2.629 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns load_new_C 1 CLK PIN_P1 18 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 18; CLK Node = 'load_new_C'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { load_new_C } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns load_new_C~clkctrl 2 COMB CLKCTRL_G1 16 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G1; Fanout = 16; COMB Node = 'load_new_C~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.113 ns" { load_new_C load_new_C~clkctrl } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.150 ns) 2.629 ns i_current_time\[0\]\[0\]~490 3 REG LCCOMB_X44_Y34_N28 2 " "Info: 3: + IC(1.367 ns) + CELL(0.150 ns) = 2.629 ns; Loc. = LCCOMB_X44_Y34_N28; Fanout = 2; REG Node = 'i_current_time\[0\]\[0\]~490'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.517 ns" { load_new_C~clkctrl i_current_time[0][0]~490 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.149 ns ( 43.70 % ) " "Info: Total cell delay = 1.149 ns ( 43.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.480 ns ( 56.30 % ) " "Info: Total interconnect delay = 1.480 ns ( 56.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.629 ns" { load_new_C load_new_C~clkctrl i_current_time[0][0]~490 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.629 ns" { load_new_C load_new_C~combout load_new_C~clkctrl i_current_time[0][0]~490 } { 0.000ns 0.000ns 0.113ns 1.367ns } { 0.000ns 0.999ns 0.000ns 0.150ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.830 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns new_current_time\[0\]\[0\] 1 PIN PIN_C13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 2; PIN Node = 'new_current_time\[0\]\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { new_current_time[0][0] } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.413 ns) + CELL(0.438 ns) 2.830 ns i_current_time\[0\]\[0\]~490 2 REG LCCOMB_X44_Y34_N28 2 " "Info: 2: + IC(1.413 ns) + CELL(0.438 ns) = 2.830 ns; Loc. = LCCOMB_X44_Y34_N28; Fanout = 2; REG Node = 'i_current_time\[0\]\[0\]~490'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.851 ns" { new_current_time[0][0] i_current_time[0][0]~490 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.417 ns ( 50.07 % ) " "Info: Total cell delay = 1.417 ns ( 50.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.413 ns ( 49.93 % ) " "Info: Total interconnect delay = 1.413 ns ( 49.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.830 ns" { new_current_time[0][0] i_current_time[0][0]~490 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.830 ns" { new_current_time[0][0] new_current_time[0][0]~combout i_current_time[0][0]~490 } { 0.000ns 0.000ns 1.413ns } { 0.000ns 0.979ns 0.438ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.629 ns" { load_new_C load_new_C~clkctrl i_current_time[0][0]~490 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.629 ns" { load_new_C load_new_C~combout load_new_C~clkctrl i_current_time[0][0]~490 } { 0.000ns 0.000ns 0.113ns 1.367ns } { 0.000ns 0.999ns 0.000ns 0.150ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.830 ns" { new_current_time[0][0] i_current_time[0][0]~490 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.830 ns" { new_current_time[0][0] new_current_time[0][0]~combout i_current_time[0][0]~490 } { 0.000ns 0.000ns 1.413ns } { 0.000ns 0.979ns 0.438ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 18 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 05 11:01:49 2008 " "Info: Processing ended: Sun Oct 05 11:01:49 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}