alarm_counter.tan.qmsg

电子闹钟：基于fpga的电子闹钟设计

{ "Info" "ITDB_TSU_RESULT" "i_current_time\[3\]\[1\]~\$emulated new_current_time\[2\]\[3\] clk 7.309 ns register " "Info: tsu for register \"i_current_time\[3\]\[1\]~\$emulated\" (data pin = \"new_current_time\[2\]\[3\]\", clock pin = \"clk\") is 7.309 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.028 ns + Longest pin register " "Info: + Longest pin to register delay is 10.028 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns new_current_time\[2\]\[3\] 1 PIN PIN_B16 2 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_B16; Fanout = 2; PIN Node = 'new_current_time\[2\]\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { new_current_time[2][3] } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.748 ns) + CELL(0.438 ns) 7.036 ns i_current_time\[2\]\[3\]~5241 2 COMB LCCOMB_X48_Y34_N4 5 " "Info: 2: + IC(5.748 ns) + CELL(0.438 ns) = 7.036 ns; Loc. = LCCOMB_X48_Y34_N4; Fanout = 5; COMB Node = 'i_current_time\[2\]\[3\]~5241'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.186 ns" { new_current_time[2][3] i_current_time[2][3]~5241 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.416 ns) 7.718 ns LessThan3~97 3 COMB LCCOMB_X48_Y34_N16 3 " "Info: 3: + IC(0.266 ns) + CELL(0.416 ns) = 7.718 ns; Loc. = LCCOMB_X48_Y34_N16; Fanout = 3; COMB Node = 'LessThan3~97'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.682 ns" { i_current_time[2][3]~5241 LessThan3~97 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.270 ns) + CELL(0.414 ns) 8.402 ns Add2~73 4 COMB LCCOMB_X48_Y34_N24 2 " "Info: 4: + IC(0.270 ns) + CELL(0.414 ns) = 8.402 ns; Loc. = LCCOMB_X48_Y34_N24; Fanout = 2; COMB Node = 'Add2~73'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.684 ns" { LessThan3~97 Add2~73 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 8.812 ns Add2~74 5 COMB LCCOMB_X48_Y34_N26 1 " "Info: 5: + IC(0.000 ns) + CELL(0.410 ns) = 8.812 ns; Loc. = LCCOMB_X48_Y34_N26; Fanout = 1; COMB Node = 'Add2~74'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { Add2~73 Add2~74 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.446 ns) + CELL(0.275 ns) 9.533 ns i_current_time\[3\]\[1\]~5268 6 COMB LCCOMB_X47_Y34_N0 1 " "Info: 6: + IC(0.446 ns) + CELL(0.275 ns) = 9.533 ns; Loc. = LCCOMB_X47_Y34_N0; Fanout = 1; COMB Node = 'i_current_time\[3\]\[1\]~5268'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.721 ns" { Add2~74 i_current_time[3][1]~5268 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.261 ns) + CELL(0.150 ns) 9.944 ns i_current_time\[3\]\[1\]~5269 7 COMB LCCOMB_X47_Y34_N14 1 " "Info: 7: + IC(0.261 ns) + CELL(0.150 ns) = 9.944 ns; Loc. = LCCOMB_X47_Y34_N14; Fanout = 1; COMB Node = 'i_current_time\[3\]\[1\]~5269'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.411 ns" { i_current_time[3][1]~5268 i_current_time[3][1]~5269 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 10.028 ns i_current_time\[3\]\[1\]~\$emulated 8 REG LCFF_X47_Y34_N15 1 " "Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 10.028 ns; Loc. = LCFF_X47_Y34_N15; Fanout = 1; REG Node = 'i_current_time\[3\]\[1\]~\$emulated'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { i_current_time[3][1]~5269 i_current_time[3][1]~$emulated } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.037 ns ( 30.29 % ) " "Info: Total cell delay = 3.037 ns ( 30.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.991 ns ( 69.71 % ) " "Info: Total interconnect delay = 6.991 ns ( 69.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.028 ns" { new_current_time[2][3] i_current_time[2][3]~5241 LessThan3~97 Add2~73 Add2~74 i_current_time[3][1]~5268 i_current_time[3][1]~5269 i_current_time[3][1]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.028 ns" { new_current_time[2][3] new_current_time[2][3]~combout i_current_time[2][3]~5241 LessThan3~97 Add2~73 Add2~74 i_current_time[3][1]~5268 i_current_time[3][1]~5269 i_current_time[3][1]~$emulated } { 0.000ns 0.000ns 5.748ns 0.266ns 0.270ns 0.000ns 0.446ns 0.261ns 0.000ns } { 0.000ns 0.850ns 0.438ns 0.416ns 0.414ns 0.410ns 0.275ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.683 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.683 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.029 ns) + CELL(0.537 ns) 2.683 ns i_current_time\[3\]\[1\]~\$emulated 3 REG LCFF_X47_Y34_N15 1 " "Info: 3: + IC(1.029 ns) + CELL(0.537 ns) = 2.683 ns; Loc. = LCFF_X47_Y34_N15; Fanout = 1; REG Node = 'i_current_time\[3\]\[1\]~\$emulated'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.566 ns" { clk~clkctrl i_current_time[3][1]~$emulated } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.25 % ) " "Info: Total cell delay = 1.536 ns ( 57.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.147 ns ( 42.75 % ) " "Info: Total interconnect delay = 1.147 ns ( 42.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.683 ns" { clk clk~clkctrl i_current_time[3][1]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.683 ns" { clk clk~combout clk~clkctrl i_current_time[3][1]~$emulated } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.028 ns" { new_current_time[2][3] i_current_time[2][3]~5241 LessThan3~97 Add2~73 Add2~74 i_current_time[3][1]~5268 i_current_time[3][1]~5269 i_current_time[3][1]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.028 ns" { new_current_time[2][3] new_current_time[2][3]~combout i_current_time[2][3]~5241 LessThan3~97 Add2~73 Add2~74 i_current_time[3][1]~5268 i_current_time[3][1]~5269 i_current_time[3][1]~$emulated } { 0.000ns 0.000ns 5.748ns 0.266ns 0.270ns 0.000ns 0.446ns 0.261ns 0.000ns } { 0.000ns 0.850ns 0.438ns 0.416ns 0.414ns 0.410ns 0.275ns 0.150ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.683 ns" { clk clk~clkctrl i_current_time[3][1]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.683 ns" { clk clk~combout clk~clkctrl i_current_time[3][1]~$emulated } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "load_new_C current_time\[2\]\[1\] i_current_time\[2\]\[1\]~589 9.221 ns register " "Info: tco from clock \"load_new_C\" to destination pin \"current_time\[2\]\[1\]\" through register \"i_current_time\[2\]\[1\]~589\" is 9.221 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "load_new_C source 2.663 ns + Longest register " "Info: + Longest clock path from clock \"load_new_C\" to source register is 2.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns load_new_C 1 CLK PIN_P1 18 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 18; CLK Node = 'load_new_C'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { load_new_C } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns load_new_C~clkctrl 2 COMB CLKCTRL_G1 16 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G1; Fanout = 16; COMB Node = 'load_new_C~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.113 ns" { load_new_C load_new_C~clkctrl } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.401 ns) + CELL(0.150 ns) 2.663 ns i_current_time\[2\]\[1\]~589 3 REG LCCOMB_X49_Y34_N16 2 " "Info: 3: + IC(1.401 ns) + CELL(0.150 ns) = 2.663 ns; Loc. = LCCOMB_X49_Y34_N16; Fanout = 2; REG Node = 'i_current_time\[2\]\[1\]~589'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.551 ns" { load_new_C~clkctrl i_current_time[2][1]~589 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.149 ns ( 43.15 % ) " "Info: Total cell delay = 1.149 ns ( 43.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.514 ns ( 56.85 % ) " "Info: Total interconnect delay = 1.514 ns ( 56.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.663 ns" { load_new_C load_new_C~clkctrl i_current_time[2][1]~589 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.663 ns" { load_new_C load_new_C~combout load_new_C~clkctrl i_current_time[2][1]~589 } { 0.000ns 0.000ns 0.113ns 1.401ns } { 0.000ns 0.999ns 0.000ns 0.150ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.558 ns + Longest register pin " "Info: + Longest register to pin delay is 6.558 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i_current_time\[2\]\[1\]~589 1 REG LCCOMB_X49_Y34_N16 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X49_Y34_N16; Fanout = 2; REG Node = 'i_current_time\[2\]\[1\]~589'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { i_current_time[2][1]~589 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.188 ns) + CELL(0.420 ns) 1.608 ns i_current_time\[2\]\[1\]~5236 2 COMB LCCOMB_X47_Y34_N16 1 " "Info: 2: + IC(1.188 ns) + CELL(0.420 ns) = 1.608 ns; Loc. = LCCOMB_X47_Y34_N16; Fanout = 1; COMB Node = 'i_current_time\[2\]\[1\]~5236'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.608 ns" { i_current_time[2][1]~589 i_current_time[2][1]~5236 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.432 ns) + CELL(0.150 ns) 2.190 ns i_current_time\[2\]\[1\]~5237 3 COMB LCCOMB_X48_Y34_N12 5 " "Info: 3: + IC(0.432 ns) + CELL(0.150 ns) = 2.190 ns; Loc. = LCCOMB_X48_Y34_N12; Fanout = 5; COMB Node = 'i_current_time\[2\]\[1\]~5237'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.582 ns" { i_current_time[2][1]~5236 i_current_time[2][1]~5237 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.570 ns) + CELL(2.798 ns) 6.558 ns current_time\[2\]\[1\] 4 PIN PIN_B20 0 " "Info: 4: + IC(1.570 ns) + CELL(2.798 ns) = 6.558 ns; Loc. = PIN_B20; Fanout = 0; PIN Node = 'current_time\[2\]\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.368 ns" { i_current_time[2][1]~5237 current_time[2][1] } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.368 ns ( 51.36 % ) " "Info: Total cell delay = 3.368 ns ( 51.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.190 ns ( 48.64 % ) " "Info: Total interconnect delay = 3.190 ns ( 48.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.558 ns" { i_current_time[2][1]~589 i_current_time[2][1]~5236 i_current_time[2][1]~5237 current_time[2][1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.558 ns" { i_current_time[2][1]~589 i_current_time[2][1]~5236 i_current_time[2][1]~5237 current_time[2][1] } { 0.000ns 1.188ns 0.432ns 1.570ns } { 0.000ns 0.420ns 0.150ns 2.798ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.663 ns" { load_new_C load_new_C~clkctrl i_current_time[2][1]~589 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.663 ns" { load_new_C load_new_C~combout load_new_C~clkctrl i_current_time[2][1]~589 } { 0.000ns 0.000ns 0.113ns 1.401ns } { 0.000ns 0.999ns 0.000ns 0.150ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.558 ns" { i_current_time[2][1]~589 i_current_time[2][1]~5236 i_current_time[2][1]~5237 current_time[2][1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.558 ns" { i_current_time[2][1]~589 i_current_time[2][1]~5236 i_current_time[2][1]~5237 current_time[2][1] } { 0.000ns 1.188ns 0.432ns 1.570ns } { 0.000ns 0.420ns 0.150ns 2.798ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "new_current_time\[2\]\[1\] current_time\[2\]\[1\] 11.320 ns Longest " "Info: Longest tpd from source pin \"new_current_time\[2\]\[1\]\" to destination pin \"current_time\[2\]\[1\]\" is 11.320 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.860 ns) 0.860 ns new_current_time\[2\]\[1\] 1 PIN PIN_J16 2 " "Info: 1: + IC(0.000 ns) + CELL(0.860 ns) = 0.860 ns; Loc. = PIN_J16; Fanout = 2; PIN Node = 'new_current_time\[2\]\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { new_current_time[2][1] } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.654 ns) + CELL(0.438 ns) 6.952 ns i_current_time\[2\]\[1\]~5237 2 COMB LCCOMB_X48_Y34_N12 5 " "Info: 2: + IC(5.654 ns) + CELL(0.438 ns) = 6.952 ns; Loc. = LCCOMB_X48_Y34_N12; Fanout = 5; COMB Node = 'i_current_time\[2\]\[1\]~5237'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.092 ns" { new_current_time[2][1] i_current_time[2][1]~5237 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.570 ns) + CELL(2.798 ns) 11.320 ns current_time\[2\]\[1\] 3 PIN PIN_B20 0 " "Info: 3: + IC(1.570 ns) + CELL(2.798 ns) = 11.320 ns; Loc. = PIN_B20; Fanout = 0; PIN Node = 'current_time\[2\]\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.368 ns" { i_current_time[2][1]~5237 current_time[2][1] } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.096 ns ( 36.18 % ) " "Info: Total cell delay = 4.096 ns ( 36.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.224 ns ( 63.82 % ) " "Info: Total interconnect delay = 7.224 ns ( 63.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.320 ns" { new_current_time[2][1] i_current_time[2][1]~5237 current_time[2][1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.320 ns" { new_current_time[2][1] new_current_time[2][1]~combout i_current_time[2][1]~5237 current_time[2][1] } { 0.000ns 0.000ns 5.654ns 1.570ns } { 0.000ns 0.860ns 0.438ns 2.798ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}