alarm_counter.tan.qmsg

电子闹钟：基于fpga的电子闹钟设计

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "i_current_time\[0\]\[0\]~490 " "Warning: Node \"i_current_time\[0\]\[0\]~490\" is a latch" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i_current_time\[0\]\[2\]~512 " "Warning: Node \"i_current_time\[0\]\[2\]~512\" is a latch" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i_current_time\[0\]\[3\]~523 " "Warning: Node \"i_current_time\[0\]\[3\]~523\" is a latch" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i_current_time\[0\]\[1\]~501 " "Warning: Node \"i_current_time\[0\]\[1\]~501\" is a latch" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i_current_time\[1\]\[0\]~534 " "Warning: Node \"i_current_time\[1\]\[0\]~534\" is a latch" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i_current_time\[1\]\[1\]~545 " "Warning: Node \"i_current_time\[1\]\[1\]~545\" is a latch" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i_current_time\[1\]\[3\]~567 " "Warning: Node \"i_current_time\[1\]\[3\]~567\" is a latch" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i_current_time\[1\]\[2\]~556 " "Warning: Node \"i_current_time\[1\]\[2\]~556\" is a latch" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i_current_time\[2\]\[0\]~578 " "Warning: Node \"i_current_time\[2\]\[0\]~578\" is a latch" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i_current_time\[2\]\[3\]~611 " "Warning: Node \"i_current_time\[2\]\[3\]~611\" is a latch" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i_current_time\[2\]\[1\]~589 " "Warning: Node \"i_current_time\[2\]\[1\]~589\" is a latch" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i_current_time\[3\]\[2\]~644 " "Warning: Node \"i_current_time\[3\]\[2\]~644\" is a latch" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i_current_time\[3\]\[1\]~633 " "Warning: Node \"i_current_time\[3\]\[1\]~633\" is a latch" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i_current_time\[3\]\[3\]~655 " "Warning: Node \"i_current_time\[3\]\[3\]~655\" is a latch" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i_current_time\[2\]\[2\]~600 " "Warning: Node \"i_current_time\[2\]\[2\]~600\" is a latch" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i_current_time\[3\]\[0\]~622 " "Warning: Node \"i_current_time\[3\]\[0\]~622\" is a latch" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 30 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "load_new_C " "Info: Assuming node \"load_new_C\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 29 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register i_current_time\[3\]\[1\]~\$emulated register i_current_time\[3\]\[2\]~\$emulated 241.95 MHz 4.133 ns Internal " "Info: Clock \"clk\" has Internal fmax of 241.95 MHz between source register \"i_current_time\[3\]\[1\]~\$emulated\" and destination register \"i_current_time\[3\]\[2\]~\$emulated\" (period= 4.133 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.921 ns + Longest register register " "Info: + Longest register to register delay is 3.921 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i_current_time\[3\]\[1\]~\$emulated 1 REG LCFF_X47_Y34_N15 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X47_Y34_N15; Fanout = 1; REG Node = 'i_current_time\[3\]\[1\]~\$emulated'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { i_current_time[3][1]~$emulated } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.741 ns) + CELL(0.150 ns) 0.891 ns i_current_time\[3\]\[1\]~5244 2 COMB LCCOMB_X49_Y34_N10 1 " "Info: 2: + IC(0.741 ns) + CELL(0.150 ns) = 0.891 ns; Loc. = LCCOMB_X49_Y34_N10; Fanout = 1; COMB Node = 'i_current_time\[3\]\[1\]~5244'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.891 ns" { i_current_time[3][1]~$emulated i_current_time[3][1]~5244 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.150 ns) 1.288 ns i_current_time\[3\]\[1\]~5245 3 COMB LCCOMB_X49_Y34_N4 10 " "Info: 3: + IC(0.247 ns) + CELL(0.150 ns) = 1.288 ns; Loc. = LCCOMB_X49_Y34_N4; Fanout = 10; COMB Node = 'i_current_time\[3\]\[1\]~5245'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.397 ns" { i_current_time[3][1]~5244 i_current_time[3][1]~5245 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.725 ns) + CELL(0.275 ns) 2.288 ns i_current_time\[3\]\[0\]~5259 4 COMB LCCOMB_X47_Y34_N10 2 " "Info: 4: + IC(0.725 ns) + CELL(0.275 ns) = 2.288 ns; Loc. = LCCOMB_X47_Y34_N10; Fanout = 2; COMB Node = 'i_current_time\[3\]\[0\]~5259'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { i_current_time[3][1]~5245 i_current_time[3][0]~5259 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.281 ns) + CELL(0.438 ns) 3.007 ns i_current_time\[3\]\[0\]~5265 5 COMB LCCOMB_X47_Y34_N6 4 " "Info: 5: + IC(0.281 ns) + CELL(0.438 ns) = 3.007 ns; Loc. = LCCOMB_X47_Y34_N6; Fanout = 4; COMB Node = 'i_current_time\[3\]\[0\]~5265'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.719 ns" { i_current_time[3][0]~5259 i_current_time[3][0]~5265 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.680 ns) + CELL(0.150 ns) 3.837 ns i_current_time\[3\]\[2\]~5271 6 COMB LCCOMB_X48_Y34_N18 1 " "Info: 6: + IC(0.680 ns) + CELL(0.150 ns) = 3.837 ns; Loc. = LCCOMB_X48_Y34_N18; Fanout = 1; COMB Node = 'i_current_time\[3\]\[2\]~5271'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.830 ns" { i_current_time[3][0]~5265 i_current_time[3][2]~5271 } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.921 ns i_current_time\[3\]\[2\]~\$emulated 7 REG LCFF_X48_Y34_N19 1 " "Info: 7: + IC(0.000 ns) + CELL(0.084 ns) = 3.921 ns; Loc. = LCFF_X48_Y34_N19; Fanout = 1; REG Node = 'i_current_time\[3\]\[2\]~\$emulated'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { i_current_time[3][2]~5271 i_current_time[3][2]~$emulated } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.247 ns ( 31.80 % ) " "Info: Total cell delay = 1.247 ns ( 31.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.674 ns ( 68.20 % ) " "Info: Total interconnect delay = 2.674 ns ( 68.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.921 ns" { i_current_time[3][1]~$emulated i_current_time[3][1]~5244 i_current_time[3][1]~5245 i_current_time[3][0]~5259 i_current_time[3][0]~5265 i_current_time[3][2]~5271 i_current_time[3][2]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.921 ns" { i_current_time[3][1]~$emulated i_current_time[3][1]~5244 i_current_time[3][1]~5245 i_current_time[3][0]~5259 i_current_time[3][0]~5265 i_current_time[3][2]~5271 i_current_time[3][2]~$emulated } { 0.000ns 0.741ns 0.247ns 0.725ns 0.281ns 0.680ns 0.000ns } { 0.000ns 0.150ns 0.150ns 0.275ns 0.438ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.002 ns - Smallest " "Info: - Smallest clock skew is 0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.685 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.685 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.537 ns) 2.685 ns i_current_time\[3\]\[2\]~\$emulated 3 REG LCFF_X48_Y34_N19 1 " "Info: 3: + IC(1.031 ns) + CELL(0.537 ns) = 2.685 ns; Loc. = LCFF_X48_Y34_N19; Fanout = 1; REG Node = 'i_current_time\[3\]\[2\]~\$emulated'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.568 ns" { clk~clkctrl i_current_time[3][2]~$emulated } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.21 % ) " "Info: Total cell delay = 1.536 ns ( 57.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.149 ns ( 42.79 % ) " "Info: Total interconnect delay = 1.149 ns ( 42.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.685 ns" { clk clk~clkctrl i_current_time[3][2]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.685 ns" { clk clk~combout clk~clkctrl i_current_time[3][2]~$emulated } { 0.000ns 0.000ns 0.118ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.683 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.683 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.029 ns) + CELL(0.537 ns) 2.683 ns i_current_time\[3\]\[1\]~\$emulated 3 REG LCFF_X47_Y34_N15 1 " "Info: 3: + IC(1.029 ns) + CELL(0.537 ns) = 2.683 ns; Loc. = LCFF_X47_Y34_N15; Fanout = 1; REG Node = 'i_current_time\[3\]\[1\]~\$emulated'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.566 ns" { clk~clkctrl i_current_time[3][1]~$emulated } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.25 % ) " "Info: Total cell delay = 1.536 ns ( 57.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.147 ns ( 42.75 % ) " "Info: Total interconnect delay = 1.147 ns ( 42.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.683 ns" { clk clk~clkctrl i_current_time[3][1]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.683 ns" { clk clk~combout clk~clkctrl i_current_time[3][1]~$emulated } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.685 ns" { clk clk~clkctrl i_current_time[3][2]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.685 ns" { clk clk~combout clk~clkctrl i_current_time[3][2]~$emulated } { 0.000ns 0.000ns 0.118ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.683 ns" { clk clk~clkctrl i_current_time[3][1]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.683 ns" { clk clk~combout clk~clkctrl i_current_time[3][1]~$emulated } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.921 ns" { i_current_time[3][1]~$emulated i_current_time[3][1]~5244 i_current_time[3][1]~5245 i_current_time[3][0]~5259 i_current_time[3][0]~5265 i_current_time[3][2]~5271 i_current_time[3][2]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.921 ns" { i_current_time[3][1]~$emulated i_current_time[3][1]~5244 i_current_time[3][1]~5245 i_current_time[3][0]~5259 i_current_time[3][0]~5265 i_current_time[3][2]~5271 i_current_time[3][2]~$emulated } { 0.000ns 0.741ns 0.247ns 0.725ns 0.281ns 0.680ns 0.000ns } { 0.000ns 0.150ns 0.150ns 0.275ns 0.438ns 0.150ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.685 ns" { clk clk~clkctrl i_current_time[3][2]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.685 ns" { clk clk~combout clk~clkctrl i_current_time[3][2]~$emulated } { 0.000ns 0.000ns 0.118ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.683 ns" { clk clk~clkctrl i_current_time[3][1]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.683 ns" { clk clk~combout clk~clkctrl i_current_time[3][1]~$emulated } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}