alarm_counter.map.qmsg

电子闹钟：基于fpga的电子闹钟设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 05 11:01:13 2008 " "Info: Processing started: Sun Oct 05 11:01:13 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off alarm_counter -c alarm_counter " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off alarm_counter -c alarm_counter" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alarm_counter.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file alarm_counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 p_alarm " "Info: Found design unit 1: p_alarm" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 4 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 alarm_counter-behav " "Info: Found design unit 2: alarm_counter-behav" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 34 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 alarm_counter " "Info: Found entity 1: alarm_counter" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 27 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "alarm_counter " "Info: Elaborating entity \"alarm_counter\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "new_current_time alarm_counter.vhd(43) " "Warning (10492): VHDL Process Statement warning at alarm_counter.vhd(43): signal \"new_current_time\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 43 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IOPT_MLS_CREATED_ALOAD_CCT" "" "Info: Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state." { { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "i_current_time\[0\]\[0\] i_current_time\[0\]\[0\]~\$emulated i_current_time\[0\]\[0\]~490 " "Info: Register \"i_current_time\[0\]\[0\]\" converted into equivalent circuit using register \"i_current_time\[0\]\[0\]~\$emulated\" and latch \"i_current_time\[0\]\[0\]~490\"" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "i_current_time\[0\]\[1\] i_current_time\[0\]\[1\]~\$emulated i_current_time\[0\]\[1\]~501 " "Info: Register \"i_current_time\[0\]\[1\]\" converted into equivalent circuit using register \"i_current_time\[0\]\[1\]~\$emulated\" and latch \"i_current_time\[0\]\[1\]~501\"" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "i_current_time\[0\]\[2\] i_current_time\[0\]\[2\]~\$emulated i_current_time\[0\]\[2\]~512 " "Info: Register \"i_current_time\[0\]\[2\]\" converted into equivalent circuit using register \"i_current_time\[0\]\[2\]~\$emulated\" and latch \"i_current_time\[0\]\[2\]~512\"" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "i_current_time\[0\]\[3\] i_current_time\[0\]\[3\]~\$emulated i_current_time\[0\]\[3\]~523 " "Info: Register \"i_current_time\[0\]\[3\]\" converted into equivalent circuit using register \"i_current_time\[0\]\[3\]~\$emulated\" and latch \"i_current_time\[0\]\[3\]~523\"" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "i_current_time\[1\]\[0\] i_current_time\[1\]\[0\]~\$emulated i_current_time\[1\]\[0\]~534 " "Info: Register \"i_current_time\[1\]\[0\]\" converted into equivalent circuit using register \"i_current_time\[1\]\[0\]~\$emulated\" and latch \"i_current_time\[1\]\[0\]~534\"" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "i_current_time\[1\]\[1\] i_current_time\[1\]\[1\]~\$emulated i_current_time\[1\]\[1\]~545 " "Info: Register \"i_current_time\[1\]\[1\]\" converted into equivalent circuit using register \"i_current_time\[1\]\[1\]~\$emulated\" and latch \"i_current_time\[1\]\[1\]~545\"" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "i_current_time\[1\]\[2\] i_current_time\[1\]\[2\]~\$emulated i_current_time\[1\]\[2\]~556 " "Info: Register \"i_current_time\[1\]\[2\]\" converted into equivalent circuit using register \"i_current_time\[1\]\[2\]~\$emulated\" and latch \"i_current_time\[1\]\[2\]~556\"" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "i_current_time\[1\]\[3\] i_current_time\[1\]\[3\]~\$emulated i_current_time\[1\]\[3\]~567 " "Info: Register \"i_current_time\[1\]\[3\]\" converted into equivalent circuit using register \"i_current_time\[1\]\[3\]~\$emulated\" and latch \"i_current_time\[1\]\[3\]~567\"" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "i_current_time\[2\]\[0\] i_current_time\[2\]\[0\]~\$emulated i_current_time\[2\]\[0\]~578 " "Info: Register \"i_current_time\[2\]\[0\]\" converted into equivalent circuit using register \"i_current_time\[2\]\[0\]~\$emulated\" and latch \"i_current_time\[2\]\[0\]~578\"" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "i_current_time\[2\]\[1\] i_current_time\[2\]\[1\]~\$emulated i_current_time\[2\]\[1\]~589 " "Info: Register \"i_current_time\[2\]\[1\]\" converted into equivalent circuit using register \"i_current_time\[2\]\[1\]~\$emulated\" and latch \"i_current_time\[2\]\[1\]~589\"" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "i_current_time\[2\]\[2\] i_current_time\[2\]\[2\]~\$emulated i_current_time\[2\]\[2\]~600 " "Info: Register \"i_current_time\[2\]\[2\]\" converted into equivalent circuit using register \"i_current_time\[2\]\[2\]~\$emulated\" and latch \"i_current_time\[2\]\[2\]~600\"" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "i_current_time\[2\]\[3\] i_current_time\[2\]\[3\]~\$emulated i_current_time\[2\]\[3\]~611 " "Info: Register \"i_current_time\[2\]\[3\]\" converted into equivalent circuit using register \"i_current_time\[2\]\[3\]~\$emulated\" and latch \"i_current_time\[2\]\[3\]~611\"" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "i_current_time\[3\]\[0\] i_current_time\[3\]\[0\]~\$emulated i_current_time\[3\]\[0\]~622 " "Info: Register \"i_current_time\[3\]\[0\]\" converted into equivalent circuit using register \"i_current_time\[3\]\[0\]~\$emulated\" and latch \"i_current_time\[3\]\[0\]~622\"" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "i_current_time\[3\]\[1\] i_current_time\[3\]\[1\]~\$emulated i_current_time\[3\]\[1\]~633 " "Info: Register \"i_current_time\[3\]\[1\]\" converted into equivalent circuit using register \"i_current_time\[3\]\[1\]~\$emulated\" and latch \"i_current_time\[3\]\[1\]~633\"" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "i_current_time\[3\]\[2\] i_current_time\[3\]\[2\]~\$emulated i_current_time\[3\]\[2\]~644 " "Info: Register \"i_current_time\[3\]\[2\]\" converted into equivalent circuit using register \"i_current_time\[3\]\[2\]~\$emulated\" and latch \"i_current_time\[3\]\[2\]~644\"" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "i_current_time\[3\]\[3\] i_current_time\[3\]\[3\]~\$emulated i_current_time\[3\]\[3\]~655 " "Info: Register \"i_current_time\[3\]\[3\]\" converted into equivalent circuit using register \"i_current_time\[3\]\[3\]~\$emulated\" and latch \"i_current_time\[3\]\[3\]~655\"" {  } { { "alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 40 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0}  } {  } 0 0 "Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state." 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "121 " "Info: Implemented 121 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "19 " "Info: Implemented 19 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "86 " "Info: Implemented 86 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 05 11:01:15 2008 " "Info: Processing ended: Sun Oct 05 11:01:15 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}