alarm_counter.vhd

电子闹钟：基于fpga的电子闹钟设计

--时间计数器源程序alarm_counter.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
entity alarm_counter is
port( new_current_time : in t_clock_time;
      load_new_C : in std_logic;
      clk : in std_logic;
      reset : in std_logic;
      current_time : out t_clock_time);
end entity;
architecture behav of alarm_counter is
signal i_current_time : t_clock_time;
begin
  process(clk,reset,load_new_C)
  variable c_t : t_clock_time;
  begin
  if reset='1' then
    i_current_time<=(0,0,0,0);
  elsif load_new_C='1' then
    i_current_time<=new_current_time;
  elsif rising_edge(clk) then
    c_t :=i_current_time;
    if c_t(0)<9 then   --书上<7    程序从这开始是计时
      c_t(0) :=c_t(0)+1;
    else
      c_t(0):=0;
      if c_t(1)<5 then
        c_t(1):=c_t(1)+1;
      else
        c_t(1):=0;
        if c_t(3)<2 then
          if c_t(2)<9 then
            c_t(2):=c_t(2)+1;
          else
            c_t(2):=0;
            c_t(3):=c_t(3)+1;
          end if;
        else
          if c_t(2)<3 then
            c_t(2):=c_t(2)+1;
          else
            c_t(2):=0;
            c_t(3):=0;
          end if;
        end if;
      end if;
    end if;
    i_current_time<=c_t;
    end if;
  end process;
    current_time<=i_current_time;
end behav;