alarm_controller.fit.qmsg

电子闹钟：基于fpga的电子闹钟设计

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.477 ns register register " "Info: Estimated most critical path is register to register delay of 2.477 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter_k\[8\] 1 REG LAB_X20_Y24 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X20_Y24; Fanout = 3; REG Node = 'counter_k\[8\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { counter_k[8] } "NODE_NAME" } } { "alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.664 ns) + CELL(0.150 ns) 0.814 ns LessThan0~221 2 COMB LAB_X21_Y24 1 " "Info: 2: + IC(0.664 ns) + CELL(0.150 ns) = 0.814 ns; Loc. = LAB_X21_Y24; Fanout = 1; COMB Node = 'LessThan0~221'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.814 ns" { counter_k[8] LessThan0~221 } "NODE_NAME" } } { "alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.150 ns) 1.379 ns LessThan0~222 3 COMB LAB_X21_Y24 17 " "Info: 3: + IC(0.415 ns) + CELL(0.150 ns) = 1.379 ns; Loc. = LAB_X21_Y24; Fanout = 17; COMB Node = 'LessThan0~222'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { LessThan0~221 LessThan0~222 } "NODE_NAME" } } { "alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.660 ns) 2.477 ns counter_k\[9\] 4 REG LAB_X20_Y24 3 " "Info: 4: + IC(0.438 ns) + CELL(0.660 ns) = 2.477 ns; Loc. = LAB_X20_Y24; Fanout = 3; REG Node = 'counter_k\[9\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.098 ns" { LessThan0~222 counter_k[9] } "NODE_NAME" } } { "alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.960 ns ( 38.76 % ) " "Info: Total cell delay = 0.960 ns ( 38.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.517 ns ( 61.24 % ) " "Info: Total interconnect delay = 1.517 ns ( 61.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.477 ns" { counter_k[8] LessThan0~221 LessThan0~222 counter_k[9] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "4 " "Warning: Found 4 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "load_new_A 0 " "Info: Pin \"load_new_A\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "load_new_C 0 " "Info: Pin \"load_new_C\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "show_new_time 0 " "Info: Pin \"show_new_time\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "show_A 0 " "Info: Pin \"show_A\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "Selector0~195clkctrl " "Info: Node Selector0~195clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear count_A_end " "Info: Port clear -- assigned as a global for destination node count_A_end -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { count_A_end } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count_A_end" } } } } { "alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 50 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { count_A_end } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear counter_A\[0\] " "Info: Port clear -- assigned as a global for destination node counter_A\[0\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { counter_A[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "counter_A\[0\]" } } } } { "alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 146 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { counter_A[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Selector0~195clkctrl } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Selector0~195clkctrl" } } } } { "alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 70 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Selector0~195clkctrl } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 06 15:18:16 2008 " "Info: Processing ended: Mon Oct 06 15:18:16 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.fit.smsg " "Info: Generated suppressed messages file E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}