alarm_controller.tan.qmsg

电子闹钟：基于fpga的电子闹钟设计

{ "Info" "ITDB_TH_RESULT" "curr_state.s2 alarm_button clk 0.396 ns register " "Info: th for register \"curr_state.s2\" (data pin = \"alarm_button\", clock pin = \"clk\") is 0.396 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.680 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 39 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 39; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.026 ns) + CELL(0.537 ns) 2.680 ns curr_state.s2 3 REG LCFF_X24_Y23_N25 2 " "Info: 3: + IC(1.026 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X24_Y23_N25; Fanout = 2; REG Node = 'curr_state.s2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.563 ns" { clk~clkctrl curr_state.s2 } "NODE_NAME" } } { "alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.31 % ) " "Info: Total cell delay = 1.536 ns ( 57.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.144 ns ( 42.69 % ) " "Info: Total interconnect delay = 1.144 ns ( 42.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.680 ns" { clk clk~clkctrl curr_state.s2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.680 ns" { clk clk~combout clk~clkctrl curr_state.s2 } { 0.000ns 0.000ns 0.118ns 1.026ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.550 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.550 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns alarm_button 1 PIN PIN_C13 8 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 8; PIN Node = 'alarm_button'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { alarm_button } "NODE_NAME" } } { "alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.337 ns) + CELL(0.150 ns) 2.466 ns Selector7~19 2 COMB LCCOMB_X24_Y23_N24 2 " "Info: 2: + IC(1.337 ns) + CELL(0.150 ns) = 2.466 ns; Loc. = LCCOMB_X24_Y23_N24; Fanout = 2; COMB Node = 'Selector7~19'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.487 ns" { alarm_button Selector7~19 } "NODE_NAME" } } { "alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 70 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.550 ns curr_state.s2 3 REG LCFF_X24_Y23_N25 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.550 ns; Loc. = LCFF_X24_Y23_N25; Fanout = 2; REG Node = 'curr_state.s2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Selector7~19 curr_state.s2 } "NODE_NAME" } } { "alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.213 ns ( 47.57 % ) " "Info: Total cell delay = 1.213 ns ( 47.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.337 ns ( 52.43 % ) " "Info: Total interconnect delay = 1.337 ns ( 52.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.550 ns" { alarm_button Selector7~19 curr_state.s2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.550 ns" { alarm_button alarm_button~combout Selector7~19 curr_state.s2 } { 0.000ns 0.000ns 1.337ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.680 ns" { clk clk~clkctrl curr_state.s2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.680 ns" { clk clk~combout clk~clkctrl curr_state.s2 } { 0.000ns 0.000ns 0.118ns 1.026ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.550 ns" { alarm_button Selector7~19 curr_state.s2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.550 ns" { alarm_button alarm_button~combout Selector7~19 curr_state.s2 } { 0.000ns 0.000ns 1.337ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 06 15:18:35 2008 " "Info: Processing ended: Mon Oct 06 15:18:35 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}