alarm_controller.tan.rpt

电子闹钟：基于fpga的电子闹钟设计

; N/A   ; None         ; 7.519 ns   ; curr_state.s3 ; load_new_C    ; clk        ;
+-------+--------------+------------+---------------+---------------+------------+


+----------------------------------------------------------------------------+
; tpd                                                                        ;
+-------+-------------------+-----------------+--------------+---------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From         ; To            ;
+-------+-------------------+-----------------+--------------+---------------+
; N/A   ; None              ; 11.137 ns       ; time_button  ; load_new_C    ;
; N/A   ; None              ; 8.412 ns        ; key          ; load_new_C    ;
; N/A   ; None              ; 7.410 ns        ; alarm_button ; show_A        ;
; N/A   ; None              ; 7.336 ns        ; key          ; show_A        ;
; N/A   ; None              ; 7.289 ns        ; key          ; load_new_A    ;
; N/A   ; None              ; 7.011 ns        ; key          ; show_new_time ;
; N/A   ; None              ; 6.976 ns        ; alarm_button ; load_new_A    ;
; N/A   ; None              ; 6.736 ns        ; alarm_button ; load_new_C    ;
+-------+-------------------+-----------------+--------------+---------------+


+-----------------------------------------------------------------------------------+
; th                                                                                ;
+---------------+-------------+-----------+--------------+---------------+----------+
; Minimum Slack ; Required th ; Actual th ; From         ; To            ; To Clock ;
+---------------+-------------+-----------+--------------+---------------+----------+
; N/A           ; None        ; 0.396 ns  ; alarm_button ; curr_state.s2 ; clk      ;
; N/A           ; None        ; 0.392 ns  ; alarm_button ; curr_state.s3 ; clk      ;
; N/A           ; None        ; 0.083 ns  ; key          ; curr_state.s2 ; clk      ;
; N/A           ; None        ; -0.026 ns ; key          ; curr_state.s4 ; clk      ;
; N/A           ; None        ; -0.100 ns ; alarm_button ; curr_state.s4 ; clk      ;
; N/A           ; None        ; -0.234 ns ; alarm_button ; curr_state.s0 ; clk      ;
; N/A           ; None        ; -0.604 ns ; key          ; curr_state.s0 ; clk      ;
; N/A           ; None        ; -0.633 ns ; alarm_button ; curr_state.s1 ; clk      ;
; N/A           ; None        ; -0.907 ns ; key          ; curr_state.s1 ; clk      ;
; N/A           ; None        ; -1.284 ns ; key          ; curr_state.s3 ; clk      ;
; N/A           ; None        ; -3.885 ns ; time_button  ; curr_state.s1 ; clk      ;
; N/A           ; None        ; -4.000 ns ; time_button  ; curr_state.s0 ; clk      ;
; N/A           ; None        ; -4.009 ns ; time_button  ; curr_state.s3 ; clk      ;
+---------------+-------------+-----------+--------------+---------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Oct 06 15:18:35 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off alarm_controller -c alarm_controller --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 335.01 MHz between source register "counter_A[12]" and destination register "counter_A[7]" (period= 2.985 ns)
    Info: + Longest register to register delay is 2.771 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y23_N25; Fanout = 3; REG Node = 'counter_A[12]'
        Info: 2: + IC(0.740 ns) + CELL(0.275 ns) = 1.015 ns; Loc. = LCCOMB_X23_Y23_N22; Fanout = 1; COMB Node = 'LessThan1~218'
        Info: 3: + IC(0.259 ns) + CELL(0.419 ns) = 1.693 ns; Loc. = LCCOMB_X23_Y23_N2; Fanout = 17; COMB Node = 'LessThan1~222'
        Info: 4: + IC(0.418 ns) + CELL(0.660 ns) = 2.771 ns; Loc. = LCFF_X22_Y23_N15; Fanout = 3; REG Node = 'counter_A[7]'
        Info: Total cell delay = 1.354 ns ( 48.86 % )
        Info: Total interconnect delay = 1.417 ns ( 51.14 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.678 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 39; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.024 ns) + CELL(0.537 ns) = 2.678 ns; Loc. = LCFF_X22_Y23_N15; Fanout = 3; REG Node = 'counter_A[7]'
            Info: Total cell delay = 1.536 ns ( 57.36 % )
            Info: Total interconnect delay = 1.142 ns ( 42.64 % )
        Info: - Longest clock path from clock "clk" to source register is 2.678 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 39; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.024 ns) + CELL(0.537 ns) = 2.678 ns; Loc. = LCFF_X22_Y23_N25; Fanout = 3; REG Node = 'counter_A[12]'
            Info: Total cell delay = 1.536 ns ( 57.36 % )
            Info: Total interconnect delay = 1.142 ns ( 42.64 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "curr_state.s3" (data pin = "time_button", clock pin = "clk") is 4.239 ns
    Info: + Longest pin to register delay is 6.955 ns
        Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_C12; Fanout = 4; PIN Node = 'time_button'
        Info: 2: + IC(5.611 ns) + CELL(0.420 ns) = 6.871 ns; Loc. = LCCOMB_X24_Y23_N4; Fanout = 2; COMB Node = 'Selector8~12'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.955 ns; Loc. = LCFF_X24_Y23_N5; Fanout = 2; REG Node = 'curr_state.s3'
        Info: Total cell delay = 1.344 ns ( 19.32 % )
        Info: Total interconnect delay = 5.611 ns ( 80.68 % )
    Info: + Micro setup delay of destination