alarm_clock.tan.qmsg

电子闹钟：基于fpga的电子闹钟设计

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "alarm_controller:u3\|curr_state.s3 alarm_counter:u4\|i_current_time\[2\]\[2\]~\$emulated clk 243 ps " "Info: Found hold time violation between source  pin or register \"alarm_controller:u3\|curr_state.s3\" and destination pin or register \"alarm_counter:u4\|i_current_time\[2\]\[2\]~\$emulated\" for clock \"clk\" (Hold time is 243 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.446 ns + Largest " "Info: + Largest clock skew is 2.446 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.099 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 5.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 87 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 87; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.787 ns) 2.927 ns fq_divider:u7\|clk 3 REG LCFF_X1_Y18_N13 2 " "Info: 3: + IC(1.023 ns) + CELL(0.787 ns) = 2.927 ns; Loc. = LCFF_X1_Y18_N13; Fanout = 2; REG Node = 'fq_divider:u7\|clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.810 ns" { clk~clkctrl fq_divider:u7|clk } "NODE_NAME" } } { "fq_divider/fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.000 ns) 3.553 ns fq_divider:u7\|clk~clkctrl 4 COMB CLKCTRL_G3 16 " "Info: 4: + IC(0.626 ns) + CELL(0.000 ns) = 3.553 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'fq_divider:u7\|clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.626 ns" { fq_divider:u7|clk fq_divider:u7|clk~clkctrl } "NODE_NAME" } } { "fq_divider/fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.009 ns) + CELL(0.537 ns) 5.099 ns alarm_counter:u4\|i_current_time\[2\]\[2\]~\$emulated 5 REG LCFF_X42_Y8_N3 1 " "Info: 5: + IC(1.009 ns) + CELL(0.537 ns) = 5.099 ns; Loc. = LCFF_X42_Y8_N3; Fanout = 1; REG Node = 'alarm_counter:u4\|i_current_time\[2\]\[2\]~\$emulated'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.546 ns" { fq_divider:u7|clk~clkctrl alarm_counter:u4|i_current_time[2][2]~$emulated } "NODE_NAME" } } { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 45.56 % ) " "Info: Total cell delay = 2.323 ns ( 45.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.776 ns ( 54.44 % ) " "Info: Total interconnect delay = 2.776 ns ( 54.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.099 ns" { clk clk~clkctrl fq_divider:u7|clk fq_divider:u7|clk~clkctrl alarm_counter:u4|i_current_time[2][2]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.099 ns" { clk clk~combout clk~clkctrl fq_divider:u7|clk fq_divider:u7|clk~clkctrl alarm_counter:u4|i_current_time[2][2]~$emulated } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.009ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.653 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.653 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 87 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 87; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.999 ns) + CELL(0.537 ns) 2.653 ns alarm_controller:u3\|curr_state.s3 3 REG LCFF_X40_Y9_N5 2 " "Info: 3: + IC(0.999 ns) + CELL(0.537 ns) = 2.653 ns; Loc. = LCFF_X40_Y9_N5; Fanout = 2; REG Node = 'alarm_controller:u3\|curr_state.s3'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.536 ns" { clk~clkctrl alarm_controller:u3|curr_state.s3 } "NODE_NAME" } } { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.90 % ) " "Info: Total cell delay = 1.536 ns ( 57.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.117 ns ( 42.10 % ) " "Info: Total interconnect delay = 1.117 ns ( 42.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.653 ns" { clk clk~clkctrl alarm_controller:u3|curr_state.s3 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.653 ns" { clk clk~combout clk~clkctrl alarm_controller:u3|curr_state.s3 } { 0.000ns 0.000ns 0.118ns 0.999ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.099 ns" { clk clk~clkctrl fq_divider:u7|clk fq_divider:u7|clk~clkctrl alarm_counter:u4|i_current_time[2][2]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.099 ns" { clk clk~combout clk~clkctrl fq_divider:u7|clk fq_divider:u7|clk~clkctrl alarm_counter:u4|i_current_time[2][2]~$emulated } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.009ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.653 ns" { clk clk~clkctrl alarm_controller:u3|curr_state.s3 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.653 ns" { clk clk~combout clk~clkctrl alarm_controller:u3|curr_state.s3 } { 0.000ns 0.000ns 0.118ns 0.999ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.219 ns - Shortest register register " "Info: - Shortest register to register delay is 2.219 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns alarm_controller:u3\|curr_state.s3 1 REG LCFF_X40_Y9_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X40_Y9_N5; Fanout = 2; REG Node = 'alarm_controller:u3\|curr_state.s3'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { alarm_controller:u3|curr_state.s3 } "NODE_NAME" } } { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns alarm_controller:u3\|Selector3~13 2 COMB LCCOMB_X40_Y9_N4 19 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X40_Y9_N4; Fanout = 19; COMB Node = 'alarm_controller:u3\|Selector3~13'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.323 ns" { alarm_controller:u3|curr_state.s3 alarm_controller:u3|Selector3~13 } "NODE_NAME" } } { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.003 ns) + CELL(0.275 ns) 1.601 ns alarm_counter:u4\|i_current_time\[2\]\[2\]~5048 3 COMB LCCOMB_X42_Y8_N8 6 " "Info: 3: + IC(1.003 ns) + CELL(0.275 ns) = 1.601 ns; Loc. = LCCOMB_X42_Y8_N8; Fanout = 6; COMB Node = 'alarm_counter:u4\|i_current_time\[2\]\[2\]~5048'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.278 ns" { alarm_controller:u3|Selector3~13 alarm_counter:u4|i_current_time[2][2]~5048 } "NODE_NAME" } } { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.275 ns) 2.135 ns alarm_counter:u4\|i_current_time\[2\]\[2\]~5071 4 COMB LCCOMB_X42_Y8_N2 1 " "Info: 4: + IC(0.259 ns) + CELL(0.275 ns) = 2.135 ns; Loc. = LCCOMB_X42_Y8_N2; Fanout = 1; COMB Node = 'alarm_counter:u4\|i_current_time\[2\]\[2\]~5071'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.534 ns" { alarm_counter:u4|i_current_time[2][2]~5048 alarm_counter:u4|i_current_time[2][2]~5071 } "NODE_NAME" } } { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.219 ns alarm_counter:u4\|i_current_time\[2\]\[2\]~\$emulated 5 REG LCFF_X42_Y8_N3 1 " "Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 2.219 ns; Loc. = LCFF_X42_Y8_N3; Fanout = 1; REG Node = 'alarm_counter:u4\|i_current_time\[2\]\[2\]~\$emulated'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { alarm_counter:u4|i_current_time[2][2]~5071 alarm_counter:u4|i_current_time[2][2]~$emulated } "NODE_NAME" } } { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.957 ns ( 43.13 % ) " "Info: Total cell delay = 0.957 ns ( 43.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.262 ns ( 56.87 % ) " "Info: Total interconnect delay = 1.262 ns ( 56.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.219 ns" { alarm_controller:u3|curr_state.s3 alarm_controller:u3|Selector3~13 alarm_counter:u4|i_current_time[2][2]~5048 alarm_counter:u4|i_current_time[2][2]~5071 alarm_counter:u4|i_current_time[2][2]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.219 ns" { alarm_controller:u3|curr_state.s3 alarm_controller:u3|Selector3~13 alarm_counter:u4|i_current_time[2][2]~5048 alarm_counter:u4|i_current_time[2][2]~5071 alarm_counter:u4|i_current_time[2][2]~$emulated } { 0.000ns 0.000ns 1.003ns 0.259ns 0.000ns } { 0.000ns 0.323ns 0.275ns 0.275ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.099 ns" { clk clk~clkctrl fq_divider:u7|clk fq_divider:u7|clk~clkctrl alarm_counter:u4|i_current_time[2][2]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.099 ns" { clk clk~combout clk~clkctrl fq_divider:u7|clk fq_divider:u7|clk~clkctrl alarm_counter:u4|i_current_time[2][2]~$emulated } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.009ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.653 ns" { clk clk~clkctrl alarm_controller:u3|curr_state.s3 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.653 ns" { clk clk~combout clk~clkctrl alarm_controller:u3|curr_state.s3 } { 0.000ns 0.000ns 0.118ns 0.999ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.219 ns" { alarm_controller:u3|curr_state.s3 alarm_controller:u3|Selector3~13 alarm_counter:u4|i_current_time[2][2]~5048 alarm_counter:u4|i_current_time[2][2]~5071 alarm_counter:u4|i_current_time[2][2]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.219 ns" { alarm_controller:u3|curr_state.s3 alarm_controller:u3|Selector3~13 alarm_counter:u4|i_current_time[2][2]~5048 alarm_counter:u4|i_current_time[2][2]~5071 alarm_counter:u4|i_current_time[2][2]~$emulated } { 0.000ns 0.000ns 1.003ns 0.259ns 0.000ns } { 0.000ns 0.323ns 0.275ns 0.275ns 0.084ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "key_down 16 " "Warning: Circuit may not operate. Detected 16 non-operational path(s) clocked by clock \"key_down\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "key_buffer:u2\|n_t\[0\]\[2\] alarm_counter:u4\|i_current_time\[0\]\[2\]~512 key_down 2.732 ns " "Info: Found hold time violation between source  pin or register \"key_buffer:u2\|n_t\[0\]\[2\]\" and destination pin or register \"alarm_counter:u4\|i_current_time\[0\]\[2\]~512\" for clock \"key_down\" (Hold time is 2.732 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.305 ns + Largest " "Info: + Largest clock skew is 3.305 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key_down destination 6.622 ns + Longest register " "Info: + Longest clock path from clock \"key_down\" to destination register is 6.622 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns key_down 1 CLK PIN_U3 24 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_U3; Fanout = 24; CLK Node = 'key_down'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key_down } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.955 ns) + CELL(0.150 ns) 2.947 ns alarm_controller:u3\|Selector2~20 2 COMB LCCOMB_X40_Y9_N10 1 " "Info: 2: + IC(1.955 ns) + CELL(0.150 ns) = 2.947 ns; Loc. = LCCOMB_X40_Y9_N10; Fanout = 1; COMB Node = 'alarm_controller:u3\|Selector2~20'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.105 ns" { key_down alarm_controller:u3|Selector2~20 } "NODE_NAME" } } { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.150 ns) 3.343 ns alarm_controller:u3\|Selector3~13 3 COMB LCCOMB_X40_Y9_N4 19 " "Info: 3: + IC(0.246 ns) + CELL(0.150 ns) = 3.343 ns; Loc. = LCCOMB_X40_Y9_N4; Fanout = 19; COMB Node = 'alarm_controller:u3\|Selector3~13'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.396 ns" { alarm_controller:u3|Selector2~20 alarm_controller:u3|Selector3~13 } "NODE_NAME" } } { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.773 ns) + CELL(0.000 ns) 5.116 ns alarm_controller:u3\|Selector3~13clkctrl 4 COMB CLKCTRL_G13 16 " "Info: 4: + IC(1.773 ns) + CELL(0.000 ns) = 5.116 ns; Loc. = CLKCTRL_G1