📄 alarm_clock.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register alarm_counter:u4\|i_current_time\[0\]\[2\]~512 register alarm_counter:u4\|i_current_time\[2\]\[3\]~\$emulated 82.03 MHz 12.19 ns Internal " "Info: Clock \"clk\" has Internal fmax of 82.03 MHz between source register \"alarm_counter:u4\|i_current_time\[0\]\[2\]~512\" and destination register \"alarm_counter:u4\|i_current_time\[2\]\[3\]~\$emulated\" (period= 12.19 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.057 ns + Longest register register " "Info: + Longest register to register delay is 4.057 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns alarm_counter:u4\|i_current_time\[0\]\[2\]~512 1 REG LCCOMB_X42_Y8_N20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X42_Y8_N20; Fanout = 2; REG Node = 'alarm_counter:u4\|i_current_time\[0\]\[2\]~512'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { alarm_counter:u4|i_current_time[0][2]~512 } "NODE_NAME" } } { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.690 ns) + CELL(0.438 ns) 1.128 ns alarm_counter:u4\|i_current_time\[0\]\[2\]~5031 2 COMB LCCOMB_X42_Y8_N6 1 " "Info: 2: + IC(0.690 ns) + CELL(0.438 ns) = 1.128 ns; Loc. = LCCOMB_X42_Y8_N6; Fanout = 1; COMB Node = 'alarm_counter:u4\|i_current_time\[0\]\[2\]~5031'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.128 ns" { alarm_counter:u4|i_current_time[0][2]~512 alarm_counter:u4|i_current_time[0][2]~5031 } "NODE_NAME" } } { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.248 ns) + CELL(0.150 ns) 1.526 ns alarm_counter:u4\|i_current_time\[0\]\[2\]~5032 3 COMB LCCOMB_X42_Y8_N26 5 " "Info: 3: + IC(0.248 ns) + CELL(0.150 ns) = 1.526 ns; Loc. = LCCOMB_X42_Y8_N26; Fanout = 5; COMB Node = 'alarm_counter:u4\|i_current_time\[0\]\[2\]~5032'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.398 ns" { alarm_counter:u4|i_current_time[0][2]~5031 alarm_counter:u4|i_current_time[0][2]~5032 } "NODE_NAME" } } { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.467 ns) + CELL(0.275 ns) 2.268 ns alarm_counter:u4\|LessThan0~60 4 COMB LCCOMB_X41_Y8_N30 8 " "Info: 4: + IC(0.467 ns) + CELL(0.275 ns) = 2.268 ns; Loc. = LCCOMB_X41_Y8_N30; Fanout = 8; COMB Node = 'alarm_counter:u4\|LessThan0~60'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.742 ns" { alarm_counter:u4|i_current_time[0][2]~5032 alarm_counter:u4|LessThan0~60 } "NODE_NAME" } } { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.275 ns) 3.008 ns alarm_counter:u4\|i_current_time\[2\]\[3\]~3 5 COMB LCCOMB_X42_Y8_N14 4 " "Info: 5: + IC(0.465 ns) + CELL(0.275 ns) = 3.008 ns; Loc. = LCCOMB_X42_Y8_N14; Fanout = 4; COMB Node = 'alarm_counter:u4\|i_current_time\[2\]\[3\]~3'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.740 ns" { alarm_counter:u4|LessThan0~60 alarm_counter:u4|i_current_time[2][3]~3 } "NODE_NAME" } } { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.389 ns) + CELL(0.660 ns) 4.057 ns alarm_counter:u4\|i_current_time\[2\]\[3\]~\$emulated 6 REG LCFF_X43_Y8_N27 1 " "Info: 6: + IC(0.389 ns) + CELL(0.660 ns) = 4.057 ns; Loc. = LCFF_X43_Y8_N27; Fanout = 1; REG Node = 'alarm_counter:u4\|i_current_time\[2\]\[3\]~\$emulated'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.049 ns" { alarm_counter:u4|i_current_time[2][3]~3 alarm_counter:u4|i_current_time[2][3]~$emulated } "NODE_NAME" } } { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.798 ns ( 44.32 % ) " "Info: Total cell delay = 1.798 ns ( 44.32 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.259 ns ( 55.68 % ) " "Info: Total interconnect delay = 2.259 ns ( 55.68 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.057 ns" { alarm_counter:u4|i_current_time[0][2]~512 alarm_counter:u4|i_current_time[0][2]~5031 alarm_counter:u4|i_current_time[0][2]~5032 alarm_counter:u4|LessThan0~60 alarm_counter:u4|i_current_time[2][3]~3 alarm_counter:u4|i_current_time[2][3]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.057 ns" { alarm_counter:u4|i_current_time[0][2]~512 alarm_counter:u4|i_current_time[0][2]~5031 alarm_counter:u4|i_current_time[0][2]~5032 alarm_counter:u4|LessThan0~60 alarm_counter:u4|i_current_time[2][3]~3 alarm_counter:u4|i_current_time[2][3]~$emulated } { 0.000ns 0.690ns 0.248ns 0.467ns 0.465ns 0.389ns } { 0.000ns 0.438ns 0.150ns 0.275ns 0.275ns 0.660ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.074 ns - Smallest " "Info: - Smallest clock skew is -2.074 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.100 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 87 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 87; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.787 ns) 2.927 ns fq_divider:u7\|clk 3 REG LCFF_X1_Y18_N13 2 " "Info: 3: + IC(1.023 ns) + CELL(0.787 ns) = 2.927 ns; Loc. = LCFF_X1_Y18_N13; Fanout = 2; REG Node = 'fq_divider:u7\|clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.810 ns" { clk~clkctrl fq_divider:u7|clk } "NODE_NAME" } } { "fq_divider/fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.000 ns) 3.553 ns fq_divider:u7\|clk~clkctrl 4 COMB CLKCTRL_G3 16 " "Info: 4: + IC(0.626 ns) + CELL(0.000 ns) = 3.553 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'fq_divider:u7\|clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.626 ns" { fq_divider:u7|clk fq_divider:u7|clk~clkctrl } "NODE_NAME" } } { "fq_divider/fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.010 ns) + CELL(0.537 ns) 5.100 ns alarm_counter:u4\|i_current_time\[2\]\[3\]~\$emulated 5 REG LCFF_X43_Y8_N27 1 " "Info: 5: + IC(1.010 ns) + CELL(0.537 ns) = 5.100 ns; Loc. = LCFF_X43_Y8_N27; Fanout = 1; REG Node = 'alarm_counter:u4\|i_current_time\[2\]\[3\]~\$emulated'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.547 ns" { fq_divider:u7|clk~clkctrl alarm_counter:u4|i_current_time[2][3]~$emulated } "NODE_NAME" } } { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 45.55 % ) " "Info: Total cell delay = 2.323 ns ( 45.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.777 ns ( 54.45 % ) " "Info: Total interconnect delay = 2.777 ns ( 54.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.100 ns" { clk clk~clkctrl fq_divider:u7|clk fq_divider:u7|clk~clkctrl alarm_counter:u4|i_current_time[2][3]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.100 ns" { clk clk~combout clk~clkctrl fq_divider:u7|clk fq_divider:u7|clk~clkctrl alarm_counter:u4|i_current_time[2][3]~$emulated } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.010ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.174 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 87 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 87; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.999 ns) + CELL(0.787 ns) 2.903 ns alarm_controller:u3\|curr_state.s1 3 REG LCFF_X40_Y9_N15 6 " "Info: 3: + IC(0.999 ns) + CELL(0.787 ns) = 2.903 ns; Loc. = LCFF_X40_Y9_N15; Fanout = 6; REG Node = 'alarm_controller:u3\|curr_state.s1'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.786 ns" { clk~clkctrl alarm_controller:u3|curr_state.s1 } "NODE_NAME" } } { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.321 ns) + CELL(0.275 ns) 3.499 ns alarm_controller:u3\|Selector2~20 4 COMB LCCOMB_X40_Y9_N10 1 " "Info: 4: + IC(0.321 ns) + CELL(0.275 ns) = 3.499 ns; Loc. = LCCOMB_X40_Y9_N10; Fanout = 1; COMB Node = 'alarm_controller:u3\|Selector2~20'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.596 ns" { alarm_controller:u3|curr_state.s1 alarm_controller:u3|Selector2~20 } "NODE_NAME" } } { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.150 ns) 3.895 ns alarm_controller:u3\|Selector3~13 5 COMB LCCOMB_X40_Y9_N4 19 " "Info: 5: + IC(0.246 ns) + CELL(0.150 ns) = 3.895 ns; Loc. = LCCOMB_X40_Y9_N4; Fanout = 19; COMB Node = 'alarm_controller:u3\|Selector3~13'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.396 ns" { alarm_controller:u3|Selector2~20 alarm_controller:u3|Selector3~13 } "NODE_NAME" } } { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.773 ns) + CELL(0.000 ns) 5.668 ns alarm_controller:u3\|Selector3~13clkctrl 6 COMB CLKCTRL_G13 16 " "Info: 6: + IC(1.773 ns) + CELL(0.000 ns) = 5.668 ns; Loc. = CLKCTRL_G13; Fanout = 16; COMB Node = 'alarm_controller:u3\|Selector3~13clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.773 ns" { alarm_controller:u3|Selector3~13 alarm_controller:u3|Selector3~13clkctrl } "NODE_NAME" } } { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.356 ns) + CELL(0.150 ns) 7.174 ns alarm_counter:u4\|i_current_time\[0\]\[2\]~512 7 REG LCCOMB_X42_Y8_N20 2 " "Info: 7: + IC(1.356 ns) + CELL(0.150 ns) = 7.174 ns; Loc. = LCCOMB_X42_Y8_N20; Fanout = 2; REG Node = 'alarm_counter:u4\|i_current_time\[0\]\[2\]~512'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.506 ns" { alarm_controller:u3|Selector3~13clkctrl alarm_counter:u4|i_current_time[0][2]~512 } "NODE_NAME" } } { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.361 ns ( 32.91 % ) " "Info: Total cell delay = 2.361 ns ( 32.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.813 ns ( 67.09 % ) " "Info: Total interconnect delay = 4.813 ns ( 67.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.174 ns" { clk clk~clkctrl alarm_controller:u3|curr_state.s1 alarm_controller:u3|Selector2~20 alarm_controller:u3|Selector3~13 alarm_controller:u3|Selector3~13clkctrl alarm_counter:u4|i_current_time[0][2]~512 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.174 ns" { clk clk~combout clk~clkctrl alarm_controller:u3|curr_state.s1 alarm_controller:u3|Selector2~20 alarm_controller:u3|Selector3~13 alarm_controller:u3|Selector3~13clkctrl alarm_counter:u4|i_current_time[0][2]~512 } { 0.000ns 0.000ns 0.118ns 0.999ns 0.321ns 0.246ns 1.773ns 1.356ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.275ns 0.150ns 0.000ns 0.150ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.100 ns" { clk clk~clkctrl fq_divider:u7|clk fq_divider:u7|clk~clkctrl alarm_counter:u4|i_current_time[2][3]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.100 ns" { clk clk~combout clk~clkctrl fq_divider:u7|clk fq_divider:u7|clk~clkctrl alarm_counter:u4|i_current_time[2][3]~$emulated } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.010ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.174 ns" { clk clk~clkctrl alarm_controller:u3|curr_state.s1 alarm_controller:u3|Selector2~20 alarm_controller:u3|Selector3~13 alarm_controller:u3|Selector3~13clkctrl alarm_counter:u4|i_current_time[0][2]~512 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.174 ns" { clk clk~combout clk~clkctrl alarm_controller:u3|curr_state.s1 alarm_controller:u3|Selector2~20 alarm_controller:u3|Selector3~13 alarm_controller:u3|Selector3~13clkctrl alarm_counter:u4|i_current_time[0][2]~512 } { 0.000ns 0.000ns 0.118ns 0.999ns 0.321ns 0.246ns 1.773ns 1.356ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.275ns 0.150ns 0.000ns 0.150ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" { } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } } { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.057 ns" { alarm_counter:u4|i_current_time[0][2]~512 alarm_counter:u4|i_current_time[0][2]~5031 alarm_counter:u4|i_current_time[0][2]~5032 alarm_counter:u4|LessThan0~60 alarm_counter:u4|i_current_time[2][3]~3 alarm_counter:u4|i_current_time[2][3]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.057 ns" { alarm_counter:u4|i_current_time[0][2]~512 alarm_counter:u4|i_current_time[0][2]~5031 alarm_counter:u4|i_current_time[0][2]~5032 alarm_counter:u4|LessThan0~60 alarm_counter:u4|i_current_time[2][3]~3 alarm_counter:u4|i_current_time[2][3]~$emulated } { 0.000ns 0.690ns 0.248ns 0.467ns 0.465ns 0.389ns } { 0.000ns 0.438ns 0.150ns 0.275ns 0.275ns 0.660ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.100 ns" { clk clk~clkctrl fq_divider:u7|clk fq_divider:u7|clk~clkctrl alarm_counter:u4|i_current_time[2][3]~$emulated } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.100 ns" { clk clk~combout clk~clkctrl fq_divider:u7|clk fq_divider:u7|clk~clkctrl alarm_counter:u4|i_current_time[2][3]~$emulated } { 0.000ns 0.000ns 0.118ns 1.023ns 0.626ns 1.010ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.174 ns" { clk clk~clkctrl alarm_controller:u3|curr_state.s1 alarm_controller:u3|Selector2~20 alarm_controller:u3|Selector3~13 alarm_controller:u3|Selector3~13clkctrl alarm_counter:u4|i_current_time[0][2]~512 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.174 ns" { clk clk~combout clk~clkctrl alarm_controller:u3|curr_state.s1 alarm_controller:u3|Selector2~20 alarm_controller:u3|Selector3~13 alarm_controller:u3|Selector3~13clkctrl alarm_counter:u4|i_current_time[0][2]~512 } { 0.000ns 0.000ns 0.118ns 0.999ns 0.321ns 0.246ns 1.773ns 1.356ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.275ns 0.150ns 0.000ns 0.150ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "key_down register register key_buffer:u2\|n_t\[0\]\[3\] key_buffer:u2\|n_t\[1\]\[3\] 450.05 MHz Internal " "Info: Clock \"key_down\" Internal fmax is restricted to 450.05 MHz between source register \"key_buffer:u2\|n_t\[0\]\[3\]\" and destination register \"key_buffer:u2\|n_t\[1\]\[3\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.222 ns " "Info: fmax restricted to clock pin edge rate 2.222 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.110 ns + Longest register register " "Info: + Longest register to register delay is 1.110 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_buffer:u2\|n_t\[0\]\[3\] 1 REG LCFF_X37_Y8_N13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X37_Y8_N13; Fanout = 5; REG Node = 'key_buffer:u2\|n_t\[0\]\[3\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key_buffer:u2|n_t[0][3] } "NODE_NAME" } } { "key_buffer/key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.744 ns) + CELL(0.366 ns) 1.110 ns key_buffer:u2\|n_t\[1\]\[3\] 2 REG LCFF_X40_Y8_N21 5 " "Info: 2: + IC(0.744 ns) + CELL(0.366 ns) = 1.110 ns; Loc. = LCFF_X40_Y8_N21; Fanout = 5; REG Node = 'key_buffer:u2\|n_t\[1\]\[3\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.110 ns" { key_buffer:u2|n_t[0][3] key_buffer:u2|n_t[1][3] } "NODE_NAME" } } { "key_buffer/key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.366 ns ( 32.97 % ) " "Info: Total cell delay = 0.366 ns ( 32.97 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.744 ns ( 67.03 % ) " "Info: Total interconnect delay = 0.744 ns ( 67.03 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.110 ns" { key_buffer:u2|n_t[0][3] key_buffer:u2|n_t[1][3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.110 ns" { key_buffer:u2|n_t[0][3] key_buffer:u2|n_t[1][3] } { 0.000ns 0.744ns } { 0.000ns 0.366ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.020 ns - Smallest " "Info: - Smallest clock skew is 0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key_down destination 3.330 ns + Shortest register " "Info: + Shortest clock path from clock \"key_down\" to destination register is 3.330 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns key_down 1 CLK PIN_U3 24 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_U3; Fanout = 24; CLK Node = 'key_down'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key_down } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.951 ns) + CELL(0.537 ns) 3.330 ns key_buffer:u2\|n_t\[1\]\[3\] 2 REG LCFF_X40_Y8_N21 5 " "Info: 2: + IC(1.951 ns) + CELL(0.537 ns) = 3.330 ns; Loc. = LCFF_X40_Y8_N21; Fanout = 5; REG Node = 'key_buffer:u2\|n_t\[1\]\[3\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.488 ns" { key_down key_buffer:u2|n_t[1][3] } "NODE_NAME" } } { "key_buffer/key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.379 ns ( 41.41 % ) " "Info: Total cell delay = 1.379 ns ( 41.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.951 ns ( 58.59 % ) " "Info: Total interconnect delay = 1.951 ns ( 58.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.330 ns" { key_down key_buffer:u2|n_t[1][3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.330 ns" { key_down key_down~combout key_buffer:u2|n_t[1][3] } { 0.000ns 0.000ns 1.951ns } { 0.000ns 0.842ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key_down source 3.310 ns - Longest register " "Info: - Longest clock path from clock \"key_down\" to source register is 3.310 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns key_down 1 CLK PIN_U3 24 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_U3; Fanout = 24; CLK Node = 'key_down'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key_down } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.931 ns) + CELL(0.537 ns) 3.310 ns key_buffer:u2\|n_t\[0\]\[3\] 2 REG LCFF_X37_Y8_N13 5 " "Info: 2: + IC(1.931 ns) + CELL(0.537 ns) = 3.310 ns; Loc. = LCFF_X37_Y8_N13; Fanout = 5; REG Node = 'key_buffer:u2\|n_t\[0\]\[3\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.468 ns" { key_down key_buffer:u2|n_t[0][3] } "NODE_NAME" } } { "key_buffer/key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.379 ns ( 41.66 % ) " "Info: Total cell delay = 1.379 ns ( 41.66 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.931 ns ( 58.34 % ) " "Info: Total interconnect delay = 1.931 ns ( 58.34 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.310 ns" { key_down key_buffer:u2|n_t[0][3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.310 ns" { key_down key_down~combout key_buffer:u2|n_t[0][3] } { 0.000ns 0.000ns 1.931ns } { 0.000ns 0.842ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.330 ns" { key_down key_buffer:u2|n_t[1][3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.330 ns" { key_down key_down~combout key_buffer:u2|n_t[1][3] } { 0.000ns 0.000ns 1.951ns } { 0.000ns 0.842ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.310 ns" { key_down key_buffer:u2|n_t[0][3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.310 ns" { key_down key_down~combout key_buffer:u2|n_t[0][3] } { 0.000ns 0.000ns 1.931ns } { 0.000ns 0.842ns 0.537ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "key_buffer/key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "key_buffer/key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.110 ns" { key_buffer:u2|n_t[0][3] key_buffer:u2|n_t[1][3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.110 ns" { key_buffer:u2|n_t[0][3] key_buffer:u2|n_t[1][3] } { 0.000ns 0.744ns } { 0.000ns 0.366ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.330 ns" { key_down key_buffer:u2|n_t[1][3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.330 ns" { key_down key_down~combout key_buffer:u2|n_t[1][3] } { 0.000ns 0.000ns 1.951ns } { 0.000ns 0.842ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.310 ns" { key_down key_buffer:u2|n_t[0][3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.310 ns" { key_down key_down~combout key_buffer:u2|n_t[0][3] } { 0.000ns 0.000ns 1.931ns } { 0.000ns 0.842ns 0.537ns } } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key_buffer:u2|n_t[1][3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { key_buffer:u2|n_t[1][3] } { } { } } } { "key_buffer/key_buffer.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/key_buffer/key_buffer.vhd" 16 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 4 " "Warning: Circuit may not operate. Detected 4 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
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