alarm_clock.tan.qmsg

电子闹钟：基于fpga的电子闹钟设计

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "alarm_counter:u4\|i_current_time\[0\]\[0\]~490 " "Warning: Node \"alarm_counter:u4\|i_current_time\[0\]\[0\]~490\" is a latch" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "alarm_counter:u4\|i_current_time\[0\]\[1\]~501 " "Warning: Node \"alarm_counter:u4\|i_current_time\[0\]\[1\]~501\" is a latch" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "alarm_counter:u4\|i_current_time\[0\]\[3\]~523 " "Warning: Node \"alarm_counter:u4\|i_current_time\[0\]\[3\]~523\" is a latch" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "alarm_counter:u4\|i_current_time\[0\]\[2\]~512 " "Warning: Node \"alarm_counter:u4\|i_current_time\[0\]\[2\]~512\" is a latch" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "alarm_counter:u4\|i_current_time\[1\]\[0\]~534 " "Warning: Node \"alarm_counter:u4\|i_current_time\[1\]\[0\]~534\" is a latch" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "alarm_counter:u4\|i_current_time\[1\]\[2\]~556 " "Warning: Node \"alarm_counter:u4\|i_current_time\[1\]\[2\]~556\" is a latch" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "alarm_counter:u4\|i_current_time\[1\]\[3\]~567 " "Warning: Node \"alarm_counter:u4\|i_current_time\[1\]\[3\]~567\" is a latch" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "alarm_counter:u4\|i_current_time\[1\]\[1\]~545 " "Warning: Node \"alarm_counter:u4\|i_current_time\[1\]\[1\]~545\" is a latch" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "alarm_counter:u4\|i_current_time\[2\]\[0\]~578 " "Warning: Node \"alarm_counter:u4\|i_current_time\[2\]\[0\]~578\" is a latch" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "alarm_counter:u4\|i_current_time\[2\]\[3\]~611 " "Warning: Node \"alarm_counter:u4\|i_current_time\[2\]\[3\]~611\" is a latch" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "alarm_counter:u4\|i_current_time\[2\]\[2\]~600 " "Warning: Node \"alarm_counter:u4\|i_current_time\[2\]\[2\]~600\" is a latch" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "alarm_counter:u4\|i_current_time\[2\]\[1\]~589 " "Warning: Node \"alarm_counter:u4\|i_current_time\[2\]\[1\]~589\" is a latch" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "alarm_counter:u4\|i_current_time\[3\]\[1\]~633 " "Warning: Node \"alarm_counter:u4\|i_current_time\[3\]\[1\]~633\" is a latch" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "alarm_counter:u4\|i_current_time\[3\]\[2\]~644 " "Warning: Node \"alarm_counter:u4\|i_current_time\[3\]\[2\]~644\" is a latch" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "alarm_counter:u4\|i_current_time\[3\]\[3\]~655 " "Warning: Node \"alarm_counter:u4\|i_current_time\[3\]\[3\]~655\" is a latch" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "alarm_counter:u4\|i_current_time\[3\]\[0\]~622 " "Warning: Node \"alarm_counter:u4\|i_current_time\[3\]\[0\]~622\" is a latch" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "alarm_clock.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "key_down " "Info: Assuming node \"key_down\" is an undefined clock" {  } { { "alarm_clock.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 32 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "key_down" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "time_button " "Info: Assuming node \"time_button\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "alarm_clock.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 34 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "alarm_button " "Info: Assuming node \"alarm_button\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "alarm_clock.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 33 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fq_divider:u7\|clk " "Info: Detected ripple clock \"fq_divider:u7\|clk\" as buffer" {  } { { "fq_divider/fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 19 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fq_divider:u7\|clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "alarm_controller:u3\|Selector2~20 " "Info: Detected gated clock \"alarm_controller:u3\|Selector2~20\" as buffer" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 50 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "alarm_controller:u3\|Selector2~20" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "alarm_controller:u3\|Selector3~13 " "Info: Detected gated clock \"alarm_controller:u3\|Selector3~13\" as buffer" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 50 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "alarm_controller:u3\|Selector3~13" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "alarm_controller:u3\|curr_state.s3 " "Info: Detected ripple clock \"alarm_controller:u3\|curr_state.s3\" as buffer" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 34 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "alarm_controller:u3\|curr_state.s3" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "alarm_controller:u3\|curr_state.s1 " "Info: Detected ripple clock \"alarm_controller:u3\|curr_state.s1\" as buffer" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 34 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "alarm_controller:u3\|curr_state.s1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}