alarm_clock.map.qmsg

电子闹钟：基于fpga的电子闹钟设计

{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[2\]\[1\] display_driver.vhd(20) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for \"display_time\[2\]\[1\]\"" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[2\]\[2\] display_driver.vhd(20) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for \"display_time\[2\]\[2\]\"" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[2\]\[3\] display_driver.vhd(20) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for \"display_time\[2\]\[3\]\"" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[3\]\[0\] display_driver.vhd(20) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for \"display_time\[3\]\[0\]\"" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[3\]\[1\] display_driver.vhd(20) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for \"display_time\[3\]\[1\]\"" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[3\]\[2\] display_driver.vhd(20) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for \"display_time\[3\]\[2\]\"" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[3\]\[3\] display_driver.vhd(20) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for \"display_time\[3\]\[3\]\"" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fq_divider fq_divider:u7 " "Info: Elaborating entity \"fq_divider\" for hierarchy \"fq_divider:u7\"" {  } { { "alarm_clock.vhd" "u7" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 102 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|alarm_clock\|alarm_controller:u3\|curr_state 5 " "Info: State machine \"\|alarm_clock\|alarm_controller:u3\|curr_state\" contains 5 states" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 23 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|alarm_clock\|alarm_controller:u3\|curr_state " "Info: Selected Auto state machine encoding method for state machine \"\|alarm_clock\|alarm_controller:u3\|curr_state\"" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 23 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|alarm_clock\|alarm_controller:u3\|curr_state " "Info: Encoding result for state machine \"\|alarm_clock\|alarm_controller:u3\|curr_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "alarm_controller:u3\|curr_state.s4 " "Info: Encoded state bit \"alarm_controller:u3\|curr_state.s4\"" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 34 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "alarm_controller:u3\|curr_state.s3 " "Info: Encoded state bit \"alarm_controller:u3\|curr_state.s3\"" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 34 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "alarm_controller:u3\|curr_state.s2 " "Info: Encoded state bit \"alarm_controller:u3\|curr_state.s2\"" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 34 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "alarm_controller:u3\|curr_state.s1 " "Info: Encoded state bit \"alarm_controller:u3\|curr_state.s1\"" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 34 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "alarm_controller:u3\|curr_state.s0 " "Info: Encoded state bit \"alarm_controller:u3\|curr_state.s0\"" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 34 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|alarm_clock\|alarm_controller:u3\|curr_state.s0 00000 " "Info: State \"\|alarm_clock\|alarm_controller:u3\|curr_state.s0\" uses code string \"00000\"" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 34 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|alarm_clock\|alarm_controller:u3\|curr_state.s1 00011 " "Info: State \"\|alarm_clock\|alarm_controller:u3\|curr_state.s1\" uses code string \"00011\"" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 34 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|alarm_clock\|alarm_controller:u3\|curr_state.s2 00101 " "Info: State \"\|alarm_clock\|alarm_controller:u3\|curr_state.s2\" uses code string \"00101\"" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 34 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|alarm_clock\|alarm_controller:u3\|curr_state.s3 01001 " "Info: State \"\|alarm_clock\|alarm_controller:u3\|curr_state.s3\" uses code string \"01001\"" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 34 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|alarm_clock\|alarm_controller:u3\|curr_state.s4 10001 " "Info: State \"\|alarm_clock\|alarm_controller:u3\|curr_state.s4\" uses code string \"10001\"" {  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 34 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "alarm_controller/alarm_controller.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_controller/alarm_controller.vhd" 23 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_CREATED_ALOAD_CCT" "" "Info: Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state." { { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "alarm_counter:u4\|i_current_time\[0\]\[0\] alarm_counter:u4\|i_current_time\[0\]\[0\]~\$emulated alarm_counter:u4\|i_current_time\[0\]\[0\]~490 " "Info: Register \"alarm_counter:u4\|i_current_time\[0\]\[0\]\" converted into equivalent circuit using register \"alarm_counter:u4\|i_current_time\[0\]\[0\]~\$emulated\" and latch \"alarm_counter:u4\|i_current_time\[0\]\[0\]~490\"" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "alarm_counter:u4\|i_current_time\[0\]\[1\] alarm_counter:u4\|i_current_time\[0\]\[1\]~\$emulated alarm_counter:u4\|i_current_time\[0\]\[1\]~501 " "Info: Register \"alarm_counter:u4\|i_current_time\[0\]\[1\]\" converted into equivalent circuit using register \"alarm_counter:u4\|i_current_time\[0\]\[1\]~\$emulated\" and latch \"alarm_counter:u4\|i_current_time\[0\]\[1\]~501\"" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "alarm_counter:u4\|i_current_time\[0\]\[2\] alarm_counter:u4\|i_current_time\[0\]\[2\]~\$emulated alarm_counter:u4\|i_current_time\[0\]\[2\]~512 " "Info: Register \"alarm_counter:u4\|i_current_time\[0\]\[2\]\" converted into equivalent circuit using register \"alarm_counter:u4\|i_current_time\[0\]\[2\]~\$emulated\" and latch \"alarm_counter:u4\|i_current_time\[0\]\[2\]~512\"" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "alarm_counter:u4\|i_current_time\[0\]\[3\] alarm_counter:u4\|i_current_time\[0\]\[3\]~\$emulated alarm_counter:u4\|i_current_time\[0\]\[3\]~523 " "Info: Register \"alarm_counter:u4\|i_current_time\[0\]\[3\]\" converted into equivalent circuit using register \"alarm_counter:u4\|i_current_time\[0\]\[3\]~\$emulated\" and latch \"alarm_counter:u4\|i_current_time\[0\]\[3\]~523\"" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "alarm_counter:u4\|i_current_time\[1\]\[0\] alarm_counter:u4\|i_current_time\[1\]\[0\]~\$emulated alarm_counter:u4\|i_current_time\[1\]\[0\]~534 " "Info: Register \"alarm_counter:u4\|i_current_time\[1\]\[0\]\" converted into equivalent circuit using register \"alarm_counter:u4\|i_current_time\[1\]\[0\]~\$emulated\" and latch \"alarm_counter:u4\|i_current_time\[1\]\[0\]~534\"" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "alarm_counter:u4\|i_current_time\[1\]\[1\] alarm_counter:u4\|i_current_time\[1\]\[1\]~\$emulated alarm_counter:u4\|i_current_time\[1\]\[1\]~545 " "Info: Register \"alarm_counter:u4\|i_current_time\[1\]\[1\]\" converted into equivalent circuit using register \"alarm_counter:u4\|i_current_time\[1\]\[1\]~\$emulated\" and latch \"alarm_counter:u4\|i_current_time\[1\]\[1\]~545\"" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "alarm_counter:u4\|i_current_time\[1\]\[2\] alarm_counter:u4\|i_current_time\[1\]\[2\]~\$emulated alarm_counter:u4\|i_current_time\[1\]\[2\]~556 " "Info: Register \"alarm_counter:u4\|i_current_time\[1\]\[2\]\" converted into equivalent circuit using register \"alarm_counter:u4\|i_current_time\[1\]\[2\]~\$emulated\" and latch \"alarm_counter:u4\|i_current_time\[1\]\[2\]~556\"" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "alarm_counter:u4\|i_current_time\[1\]\[3\] alarm_counter:u4\|i_current_time\[1\]\[3\]~\$emulated alarm_counter:u4\|i_current_time\[1\]\[3\]~567 " "Info: Register \"alarm_counter:u4\|i_current_time\[1\]\[3\]\" converted into equivalent circuit using register \"alarm_counter:u4\|i_current_time\[1\]\[3\]~\$emulated\" and latch \"alarm_counter:u4\|i_current_time\[1\]\[3\]~567\"" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "alarm_counter:u4\|i_current_time\[2\]\[0\] alarm_counter:u4\|i_current_time\[2\]\[0\]~\$emulated alarm_counter:u4\|i_current_time\[2\]\[0\]~578 " "Info: Register \"alarm_counter:u4\|i_current_time\[2\]\[0\]\" converted into equivalent circuit using register \"alarm_counter:u4\|i_current_time\[2\]\[0\]~\$emulated\" and latch \"alarm_counter:u4\|i_current_time\[2\]\[0\]~578\"" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "alarm_counter:u4\|i_current_time\[2\]\[1\] alarm_counter:u4\|i_current_time\[2\]\[1\]~\$emulated alarm_counter:u4\|i_current_time\[2\]\[1\]~589 " "Info: Register \"alarm_counter:u4\|i_current_time\[2\]\[1\]\" converted into equivalent circuit using register \"alarm_counter:u4\|i_current_time\[2\]\[1\]~\$emulated\" and latch \"alarm_counter:u4\|i_current_time\[2\]\[1\]~589\"" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "alarm_counter:u4\|i_current_time\[2\]\[2\] alarm_counter:u4\|i_current_time\[2\]\[2\]~\$emulated alarm_counter:u4\|i_current_time\[2\]\[2\]~600 " "Info: Register \"alarm_counter:u4\|i_current_time\[2\]\[2\]\" converted into equivalent circuit using register \"alarm_counter:u4\|i_current_time\[2\]\[2\]~\$emulated\" and latch \"alarm_counter:u4\|i_current_time\[2\]\[2\]~600\"" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "alarm_counter:u4\|i_current_time\[2\]\[3\] alarm_counter:u4\|i_current_time\[2\]\[3\]~\$emulated alarm_counter:u4\|i_current_time\[2\]\[3\]~611 " "Info: Register \"alarm_counter:u4\|i_current_time\[2\]\[3\]\" converted into equivalent circuit using register \"alarm_counter:u4\|i_current_time\[2\]\[3\]~\$emulated\" and latch \"alarm_counter:u4\|i_current_time\[2\]\[3\]~611\"" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "alarm_counter:u4\|i_current_time\[3\]\[0\] alarm_counter:u4\|i_current_time\[3\]\[0\]~\$emulated alarm_counter:u4\|i_current_time\[3\]\[0\]~622 " "Info: Register \"alarm_counter:u4\|i_current_time\[3\]\[0\]\" converted into equivalent circuit using register \"alarm_counter:u4\|i_current_time\[3\]\[0\]~\$emulated\" and latch \"alarm_counter:u4\|i_current_time\[3\]\[0\]~622\"" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "alarm_counter:u4\|i_current_time\[3\]\[1\] alarm_counter:u4\|i_current_time\[3\]\[1\]~\$emulated alarm_counter:u4\|i_current_time\[3\]\[1\]~633 " "Info: Register \"alarm_counter:u4\|i_current_time\[3\]\[1\]\" converted into equivalent circuit using register \"alarm_counter:u4\|i_current_time\[3\]\[1\]~\$emulated\" and latch \"alarm_counter:u4\|i_current_time\[3\]\[1\]~633\"" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "alarm_counter:u4\|i_current_time\[3\]\[2\] alarm_counter:u4\|i_current_time\[3\]\[2\]~\$emulated alarm_counter:u4\|i_current_time\[3\]\[2\]~644 " "Info: Register \"alarm_counter:u4\|i_current_time\[3\]\[2\]\" converted into equivalent circuit using register \"alarm_counter:u4\|i_current_time\[3\]\[2\]~\$emulated\" and latch \"alarm_counter:u4\|i_current_time\[3\]\[2\]~644\"" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "alarm_counter:u4\|i_current_time\[3\]\[3\] alarm_counter:u4\|i_current_time\[3\]\[3\]~\$emulated alarm_counter:u4\|i_current_time\[3\]\[3\]~655 " "Info: Register \"alarm_counter:u4\|i_current_time\[3\]\[3\]\" converted into equivalent circuit using register \"alarm_counter:u4\|i_current_time\[3\]\[3\]~\$emulated\" and latch \"alarm_counter:u4\|i_current_time\[3\]\[3\]~655\"" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0}  } {  } 0 0 "Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state." 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "358 " "Info: Implemented 358 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "15 " "Info: Implemented 15 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "29 " "Info: Implemented 29 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "314 " "Info: Implemented 314 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 06 16:53:10 2008 " "Info: Processing ended: Mon Oct 06 16:53:10 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}