alarm_clock.map.qmsg

电子闹钟：基于fpga的电子闹钟设计

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alarm_controller alarm_controller:u3 " "Info: Elaborating entity \"alarm_controller\" for hierarchy \"alarm_controller:u3\"" {  } { { "alarm_clock.vhd" "u3" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 98 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alarm_counter alarm_counter:u4 " "Info: Elaborating entity \"alarm_counter\" for hierarchy \"alarm_counter:u4\"" {  } { { "alarm_clock.vhd" "u4" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 99 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "new_current_time alarm_counter.vhd(22) " "Warning (10492): VHDL Process Statement warning at alarm_counter.vhd(22): signal \"new_current_time\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "alarm_counter/alarm_counter.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_counter/alarm_counter.vhd" 22 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alarm_reg alarm_reg:u5 " "Info: Elaborating entity \"alarm_reg\" for hierarchy \"alarm_reg:u5\"" {  } { { "alarm_clock.vhd" "u5" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 100 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display_driver display_driver:u6 " "Info: Elaborating entity \"display_driver\" for hierarchy \"display_driver:u6\"" {  } { { "alarm_clock.vhd" "u6" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_clock.vhd" 101 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "display_time display_driver.vhd(20) " "Warning (10631): VHDL Process Statement warning at display_driver.vhd(20): inferring latch(es) for signal or variable \"display_time\", which holds its previous value in one or more paths through the process" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[0\]\[0\] display_driver.vhd(20) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for \"display_time\[0\]\[0\]\"" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[0\]\[1\] display_driver.vhd(20) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for \"display_time\[0\]\[1\]\"" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[0\]\[2\] display_driver.vhd(20) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for \"display_time\[0\]\[2\]\"" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[0\]\[3\] display_driver.vhd(20) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for \"display_time\[0\]\[3\]\"" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[1\]\[0\] display_driver.vhd(20) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for \"display_time\[1\]\[0\]\"" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[1\]\[1\] display_driver.vhd(20) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for \"display_time\[1\]\[1\]\"" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[1\]\[2\] display_driver.vhd(20) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for \"display_time\[1\]\[2\]\"" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[1\]\[3\] display_driver.vhd(20) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for \"display_time\[1\]\[3\]\"" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[2\]\[0\] display_driver.vhd(20) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for \"display_time\[2\]\[0\]\"" {  } { { "display_driver/display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}