fq_divider.tan.rpt

电子闹钟：基于fpga的电子闹钟设计

; N/A                                     ; 375.09 MHz ( period = 2.666 ns )                    ; cnt[15] ; clk_out~reg0 ; clk_in     ; clk_in   ; None                        ; None                      ; 2.452 ns                ;
; N/A                                     ; 375.38 MHz ( period = 2.664 ns )                    ; cnt[8]  ; cnt[13]      ; clk_in     ; clk_in   ; None                        ; None                      ; 2.450 ns                ;
; N/A                                     ; 375.38 MHz ( period = 2.664 ns )                    ; cnt[8]  ; cnt[3]       ; clk_in     ; clk_in   ; None                        ; None                      ; 2.450 ns                ;
; N/A                                     ; 375.38 MHz ( period = 2.664 ns )                    ; cnt[8]  ; cnt[2]       ; clk_in     ; clk_in   ; None                        ; None                      ; 2.450 ns                ;
; N/A                                     ; 375.38 MHz ( period = 2.664 ns )                    ; cnt[8]  ; cnt[4]       ; clk_in     ; clk_in   ; None                        ; None                      ; 2.450 ns                ;
; N/A                                     ; 375.38 MHz ( period = 2.664 ns )                    ; cnt[8]  ; cnt[1]       ; clk_in     ; clk_in   ; None                        ; None                      ; 2.450 ns                ;
; N/A                                     ; 375.38 MHz ( period = 2.664 ns )                    ; cnt[8]  ; cnt[15]      ; clk_in     ; clk_in   ; None                        ; None                      ; 2.450 ns                ;
; N/A                                     ; 375.38 MHz ( period = 2.664 ns )                    ; cnt[8]  ; cnt[14]      ; clk_in     ; clk_in   ; None                        ; None                      ; 2.450 ns                ;
; N/A                                     ; 375.38 MHz ( period = 2.664 ns )                    ; cnt[8]  ; cnt[12]      ; clk_in     ; clk_in   ; None                        ; None                      ; 2.450 ns                ;
; N/A                                     ; 375.38 MHz ( period = 2.664 ns )                    ; cnt[8]  ; cnt[9]       ; clk_in     ; clk_in   ; None                        ; None                      ; 2.450 ns                ;
; N/A                                     ; 375.38 MHz ( period = 2.664 ns )                    ; cnt[8]  ; cnt[10]      ; clk_in     ; clk_in   ; None                        ; None                      ; 2.450 ns                ;
; N/A                                     ; 375.38 MHz ( period = 2.664 ns )                    ; cnt[8]  ; cnt[11]      ; clk_in     ; clk_in   ; None                        ; None                      ; 2.450 ns                ;
; N/A                                     ; 375.38 MHz ( period = 2.664 ns )                    ; cnt[8]  ; cnt[5]       ; clk_in     ; clk_in   ; None                        ; None                      ; 2.450 ns                ;
; N/A                                     ; 375.38 MHz ( period = 2.664 ns )                    ; cnt[8]  ; cnt[7]       ; clk_in     ; clk_in   ; None                        ; None                      ; 2.450 ns                ;
; N/A                                     ; 375.38 MHz ( period = 2.664 ns )                    ; cnt[8]  ; cnt[8]       ; clk_in     ; clk_in   ; None                        ; None                      ; 2.450 ns                ;
; N/A                                     ; 375.38 MHz ( period = 2.664 ns )                    ; cnt[8]  ; cnt[6]       ; clk_in     ; clk_in   ; None                        ; None                      ; 2.450 ns                ;
; N/A                                     ; 375.38 MHz ( period = 2.664 ns )                    ; cnt[8]  ; cnt[0]       ; clk_in     ; clk_in   ; None                        ; None                      ; 2.450 ns                ;
; N/A                                     ; 375.66 MHz ( period = 2.662 ns )                    ; cnt[11] ; cnt[5]       ; clk_in     ; clk_in   ; None                        ; None                      ; 2.448 ns                ;
; N/A                                     ; 375.66 MHz ( period = 2.662 ns )                    ; cnt[11] ; cnt[7]       ; clk_in     ; clk_in   ; None                        ; None                      ; 2.448 ns                ;
; N/A                                     ; 375.66 MHz ( period = 2.662 ns )                    ; cnt[11] ; cnt[8]       ; clk_in     ; clk_in   ; None                        ; None                      ; 2.448 ns                ;
; N/A                                     ; 375.66 MHz ( period = 2.662 ns )                    ; cnt[11] ; cnt[6]       ; clk_in     ; clk_in   ; None                        ; None                      ; 2.448 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;         ;              ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 6.252 ns   ; clk_out~reg0 ; clk_out ; clk_in     ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Oct 05 14:54:10 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fq_divider -c fq_divider --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk_in" is an undefined clock
Info: Clock "clk_in" has Internal fmax of 318.27 MHz between source register "cnt[12]" and destination register "cnt[13]" (period= 3.142 ns)
    Info: + Longest register to register delay is 2.928 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y13_N25; Fanout = 3; REG Node = 'cnt[12]'
        Info: 2: + IC(0.725 ns) + CELL(0.398 ns) = 1.123 ns; Loc. = LCCOMB_X63_Y13_N16; Fanout = 1; COMB Node = 'LessThan1~373'
        Info: 3: + IC(0.247 ns) + CELL(0.275 ns) = 1.645 ns; Loc. = LCCOMB_X63_Y13_N18; Fanout = 2; COMB Node = 'LessThan1~375'
        Info: 4: + IC(0.251 ns) + CELL(0.150 ns) = 2.046 ns; Loc. = LCCOMB_X63_Y13_N30; Fanout = 17; COMB Node = 'LessThan1~377'
        Info: 5: + IC(0.372 ns) + CELL(0.510 ns) = 2.928 ns; Loc. = LCFF_X64_Y13_N27; Fanout = 3; REG Node = 'cnt[13]'
        Info: Total cell delay = 1.333 ns ( 45.53 % )
        Info: Total interconnect delay = 1.595 ns ( 54.47 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk_in" to destination register is 2.674 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 17; COMB Node = 'clk_in~clkctrl'
            Info: 3: + IC(1.020 ns) + CELL(0.537 ns) = 2.674 ns; Loc. = LCFF_X64_Y13_N27; Fanout = 3; REG Node = 'cnt[13]'
            Info: Total cell delay = 1.536 ns ( 57.44 % )
            Info: Total interconnect delay = 1.138 ns ( 42.56 % )
        Info: - Longest clock path from clock "clk_in" to source register is 2.674 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 17; COMB Node = 'clk_in~clkctrl'
            Info: 3: + IC(1.020 ns) + CELL(0.537 ns) = 2.674 ns; Loc. = LCFF_X64_Y13_N25; Fanout = 3; REG Node = 'cnt[12]'
            Info: Total cell delay = 1.536 ns ( 57.44 % )
            Info: Total interconnect delay = 1.138 ns ( 42.56 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clk_in" to destination pin "clk_out" through register "clk_out~reg0" is 6.252 ns
    Info: + Longest clock path from clock "clk_in" to source register is 2.674 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 17; COMB Node = 'clk_in~clkctrl'
        Info: 3: + IC(1.020 ns) + CELL(0.537 ns) = 2.674 ns; Loc. = LCFF_X63_Y13_N11; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 1.536 ns ( 57.44 % )
        Info: Total interconnect delay = 1.138 ns ( 42.56 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.328 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y13_N11; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: 2: + IC(0.696 ns) + CELL(2.632 ns) = 3.328 ns; Loc. = PIN_U23; Fanout = 0; PIN Node = 'clk_out'
        Info: Total cell delay = 2.632 ns ( 79.09 % )
        Info: Total interconnect delay = 0.696 ns ( 20.91 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Oct 05 14:54:11 2008
    Info: Elapsed time: 00:00:02