fq_divider.map.qmsg

电子闹钟：基于fpga的电子闹钟设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 05 15:31:19 2008 " "Info: Processing started: Sun Oct 05 15:31:19 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fq_divider -c fq_divider " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fq_divider -c fq_divider" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fq_divider.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fq_divider.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fq_divider-behav " "Info: Found design unit 1: fq_divider-behav" {  } { { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fq_divider " "Info: Found entity 1: fq_divider" {  } { { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_IS_NOT_COMPILED_IN_LIBRARY" "p_alarm work fq_divider.vhd(7) " "Error (10481): VHDL Use Clause error at fq_divider.vhd(7): design library \"work\" does not contain primary unit \"p_alarm\"" {  } { { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 7 0 0 } }  } 0 10481 "VHDL Use Clause error at %3!s!: design library \"%2!s!\" does not contain primary unit \"%1!s!\"" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Sun Oct 05 15:31:20 2008 " "Error: Processing ended: Sun Oct 05 15:31:20 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}