fq_divider.tan.qmsg

电子闹钟：基于fpga的电子闹钟设计

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_in register cnt\[12\] register cnt\[13\] 318.27 MHz 3.142 ns Internal " "Info: Clock \"clk_in\" has Internal fmax of 318.27 MHz between source register \"cnt\[12\]\" and destination register \"cnt\[13\]\" (period= 3.142 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.928 ns + Longest register register " "Info: + Longest register to register delay is 2.928 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[12\] 1 REG LCFF_X64_Y13_N25 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y13_N25; Fanout = 3; REG Node = 'cnt\[12\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt[12] } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.725 ns) + CELL(0.398 ns) 1.123 ns LessThan1~373 2 COMB LCCOMB_X63_Y13_N16 1 " "Info: 2: + IC(0.725 ns) + CELL(0.398 ns) = 1.123 ns; Loc. = LCCOMB_X63_Y13_N16; Fanout = 1; COMB Node = 'LessThan1~373'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.123 ns" { cnt[12] LessThan1~373 } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.275 ns) 1.645 ns LessThan1~375 3 COMB LCCOMB_X63_Y13_N18 2 " "Info: 3: + IC(0.247 ns) + CELL(0.275 ns) = 1.645 ns; Loc. = LCCOMB_X63_Y13_N18; Fanout = 2; COMB Node = 'LessThan1~375'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.522 ns" { LessThan1~373 LessThan1~375 } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.251 ns) + CELL(0.150 ns) 2.046 ns LessThan1~377 4 COMB LCCOMB_X63_Y13_N30 17 " "Info: 4: + IC(0.251 ns) + CELL(0.150 ns) = 2.046 ns; Loc. = LCCOMB_X63_Y13_N30; Fanout = 17; COMB Node = 'LessThan1~377'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.401 ns" { LessThan1~375 LessThan1~377 } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.510 ns) 2.928 ns cnt\[13\] 5 REG LCFF_X64_Y13_N27 3 " "Info: 5: + IC(0.372 ns) + CELL(0.510 ns) = 2.928 ns; Loc. = LCFF_X64_Y13_N27; Fanout = 3; REG Node = 'cnt\[13\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.882 ns" { LessThan1~377 cnt[13] } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.333 ns ( 45.53 % ) " "Info: Total cell delay = 1.333 ns ( 45.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.595 ns ( 54.47 % ) " "Info: Total interconnect delay = 1.595 ns ( 54.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.928 ns" { cnt[12] LessThan1~373 LessThan1~375 LessThan1~377 cnt[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.928 ns" { cnt[12] LessThan1~373 LessThan1~375 LessThan1~377 cnt[13] } { 0.000ns 0.725ns 0.247ns 0.251ns 0.372ns } { 0.000ns 0.398ns 0.275ns 0.150ns 0.510ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 2.674 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_in\" to destination register is 2.674 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_in 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_in~clkctrl 2 COMB CLKCTRL_G3 17 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 17; COMB Node = 'clk_in~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_in clk_in~clkctrl } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.020 ns) + CELL(0.537 ns) 2.674 ns cnt\[13\] 3 REG LCFF_X64_Y13_N27 3 " "Info: 3: + IC(1.020 ns) + CELL(0.537 ns) = 2.674 ns; Loc. = LCFF_X64_Y13_N27; Fanout = 3; REG Node = 'cnt\[13\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.557 ns" { clk_in~clkctrl cnt[13] } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.44 % ) " "Info: Total cell delay = 1.536 ns ( 57.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.138 ns ( 42.56 % ) " "Info: Total interconnect delay = 1.138 ns ( 42.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.674 ns" { clk_in clk_in~clkctrl cnt[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.674 ns" { clk_in clk_in~combout clk_in~clkctrl cnt[13] } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 2.674 ns - Longest register " "Info: - Longest clock path from clock \"clk_in\" to source register is 2.674 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_in 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_in~clkctrl 2 COMB CLKCTRL_G3 17 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 17; COMB Node = 'clk_in~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_in clk_in~clkctrl } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.020 ns) + CELL(0.537 ns) 2.674 ns cnt\[12\] 3 REG LCFF_X64_Y13_N25 3 " "Info: 3: + IC(1.020 ns) + CELL(0.537 ns) = 2.674 ns; Loc. = LCFF_X64_Y13_N25; Fanout = 3; REG Node = 'cnt\[12\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.557 ns" { clk_in~clkctrl cnt[12] } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.44 % ) " "Info: Total cell delay = 1.536 ns ( 57.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.138 ns ( 42.56 % ) " "Info: Total interconnect delay = 1.138 ns ( 42.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.674 ns" { clk_in clk_in~clkctrl cnt[12] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.674 ns" { clk_in clk_in~combout clk_in~clkctrl cnt[12] } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.674 ns" { clk_in clk_in~clkctrl cnt[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.674 ns" { clk_in clk_in~combout clk_in~clkctrl cnt[13] } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.674 ns" { clk_in clk_in~clkctrl cnt[12] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.674 ns" { clk_in clk_in~combout clk_in~clkctrl cnt[12] } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 39 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 39 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.928 ns" { cnt[12] LessThan1~373 LessThan1~375 LessThan1~377 cnt[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.928 ns" { cnt[12] LessThan1~373 LessThan1~375 LessThan1~377 cnt[13] } { 0.000ns 0.725ns 0.247ns 0.251ns 0.372ns } { 0.000ns 0.398ns 0.275ns 0.150ns 0.510ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.674 ns" { clk_in clk_in~clkctrl cnt[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.674 ns" { clk_in clk_in~combout clk_in~clkctrl cnt[13] } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.674 ns" { clk_in clk_in~clkctrl cnt[12] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.674 ns" { clk_in clk_in~combout clk_in~clkctrl cnt[12] } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_in clk_out clk_out~reg0 6.252 ns register " "Info: tco from clock \"clk_in\" to destination pin \"clk_out\" through register \"clk_out~reg0\" is 6.252 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 2.674 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to source register is 2.674 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_in 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_in~clkctrl 2 COMB CLKCTRL_G3 17 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 17; COMB Node = 'clk_in~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_in clk_in~clkctrl } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.020 ns) + CELL(0.537 ns) 2.674 ns clk_out~reg0 3 REG LCFF_X63_Y13_N11 2 " "Info: 3: + IC(1.020 ns) + CELL(0.537 ns) = 2.674 ns; Loc. = LCFF_X63_Y13_N11; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.557 ns" { clk_in~clkctrl clk_out~reg0 } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.44 % ) " "Info: Total cell delay = 1.536 ns ( 57.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.138 ns ( 42.56 % ) " "Info: Total interconnect delay = 1.138 ns ( 42.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.674 ns" { clk_in clk_in~clkctrl clk_out~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.674 ns" { clk_in clk_in~combout clk_in~clkctrl clk_out~reg0 } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 39 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.328 ns + Longest register pin " "Info: + Longest register to pin delay is 3.328 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_out~reg0 1 REG LCFF_X63_Y13_N11 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y13_N11; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_out~reg0 } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.696 ns) + CELL(2.632 ns) 3.328 ns clk_out 2 PIN PIN_U23 0 " "Info: 2: + IC(0.696 ns) + CELL(2.632 ns) = 3.328 ns; Loc. = PIN_U23; Fanout = 0; PIN Node = 'clk_out'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.328 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/fq_divider/fq_divider.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.632 ns ( 79.09 % ) " "Info: Total cell delay = 2.632 ns ( 79.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.696 ns ( 20.91 % ) " "Info: Total interconnect delay = 0.696 ns ( 20.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.328 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.328 ns" { clk_out~reg0 clk_out } { 0.000ns 0.696ns } { 0.000ns 2.632ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.674 ns" { clk_in clk_in~clkctrl clk_out~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.674 ns" { clk_in clk_in~combout clk_in~clkctrl clk_out~reg0 } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.328 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.328 ns" { clk_out~reg0 clk_out } { 0.000ns 0.696ns } { 0.000ns 2.632ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 05 14:54:11 2008 " "Info: Processing ended: Sun Oct 05 14:54:11 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}