fq_divider.vhd

来自「电子闹钟：基于fpga的电子闹钟设计」· VHDL 代码 · 共 29 行

 


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fq_divider is
port( clk_in : in std_logic;
      reset : in std_logic;
      clk_out : out std_logic);
end entity;
architecture behav of fq_divider is
signal tout : integer range 0 to 1500000000;
signal clk: std_logic;
begin
  process(clk_in)
  begin
    if rising_edge(clk_in) then
      if tout=1500000000 then   --计数1250000次，输出翻转一次
        tout<=0;
        clk<=not clk;
      else
        tout<=tout+1;
      end if;
    end if;
  end process;
clk_out<=clk;
end behav;