decoder.vhd

来自「电子闹钟：基于fpga的电子闹钟设计」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
entity decoder is
port( keypad : in std_logic_vector(9 downto 0);
      value : out t_digital);
end entity;
architecture behav of decoder is
begin
  with keypad select
  value<=0 when "0000000001",
         1 when "0000000010",
         2 when "0000000100",
         3 when "0000001000",
         4 when "0000010000",
         5 when "0000100000",
         6 when "0001000000",
         7 when "0010000000",
         8 when "0100000000",
         9 when "1000000000",
         0 when others;
end architecture;