display_driver.tan.qmsg

电子闹钟：基于fpga的电子闹钟设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 05 11:52:17 2008 " "Info: Processing started: Sun Oct 05 11:52:17 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off display_driver -c display_driver --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off display_driver -c display_driver --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "alarm_time\[0\]\[1\] display\[0\]\[3\] 13.832 ns Longest " "Info: Longest tpd from source pin \"alarm_time\[0\]\[1\]\" to destination pin \"display\[0\]\[3\]\" is 13.832 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns alarm_time\[0\]\[1\] 1 PIN PIN_AE16 2 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_AE16; Fanout = 2; PIN Node = 'alarm_time\[0\]\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { alarm_time[0][1] } "NODE_NAME" } } { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.592 ns) + CELL(0.420 ns) 6.852 ns comb~2051 2 COMB LCCOMB_X27_Y1_N22 1 " "Info: 2: + IC(5.592 ns) + CELL(0.420 ns) = 6.852 ns; Loc. = LCCOMB_X27_Y1_N22; Fanout = 1; COMB Node = 'comb~2051'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.012 ns" { alarm_time[0][1] comb~2051 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.248 ns) + CELL(0.420 ns) 7.520 ns comb~2052 3 COMB LCCOMB_X27_Y1_N24 7 " "Info: 3: + IC(0.248 ns) + CELL(0.420 ns) = 7.520 ns; Loc. = LCCOMB_X27_Y1_N24; Fanout = 7; COMB Node = 'comb~2052'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.668 ns" { comb~2051 comb~2052 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.984 ns) + CELL(0.410 ns) 9.914 ns Mux24~141 4 COMB LCCOMB_X7_Y4_N4 1 " "Info: 4: + IC(1.984 ns) + CELL(0.410 ns) = 9.914 ns; Loc. = LCCOMB_X7_Y4_N4; Fanout = 1; COMB Node = 'Mux24~141'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.394 ns" { comb~2052 Mux24~141 } "NODE_NAME" } } { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.256 ns) + CELL(2.662 ns) 13.832 ns display\[0\]\[3\] 5 PIN PIN_V7 0 " "Info: 5: + IC(1.256 ns) + CELL(2.662 ns) = 13.832 ns; Loc. = PIN_V7; Fanout = 0; PIN Node = 'display\[0\]\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.918 ns" { Mux24~141 display[0][3] } "NODE_NAME" } } { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.752 ns ( 34.36 % ) " "Info: Total cell delay = 4.752 ns ( 34.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.080 ns ( 65.64 % ) " "Info: Total interconnect delay = 9.080 ns ( 65.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.832 ns" { alarm_time[0][1] comb~2051 comb~2052 Mux24~141 display[0][3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "13.832 ns" { alarm_time[0][1] alarm_time[0][1]~combout comb~2051 comb~2052 Mux24~141 display[0][3] } { 0.000ns 0.000ns 5.592ns 0.248ns 1.984ns 1.256ns } { 0.000ns 0.840ns 0.420ns 0.420ns 0.410ns 2.662ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 05 11:52:17 2008 " "Info: Processing ended: Sun Oct 05 11:52:17 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}