display_driver.vhd

电子闹钟：基于fpga的电子闹钟设计

                           

--闹钟系统的显示驱动display_driver.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
entity display_driver is
port( alarm_time : in t_clock_time;
      current_time : in t_clock_time;
      new_time : in t_clock_time;
      show_new_time : in std_logic;
      show_A : in std_logic;
      sound_alarm : out std_logic;
      display : out t_display);
end entity;
architecture behav of display_driver is
signal display_time : t_clock_time;
begin
  ctrl:process(alarm_time,current_time,new_time,show_A,show_new_time) is
  begin
    sound_lp: for i in alarm_time' range loop
          if not(alarm_time(i)=current_time(i)) then
            sound_alarm<='0';
            exit sound_lp;
          else
            sound_alarm<='1';
          end if;
    end loop sound_lp;
      if show_new_time='1' then
        display_time<=new_time;
      elsif show_A='1' then
        display_time<=alarm_time;
      elsif show_A='0' then
        display_time<=current_time;
      else
        assert false report " Uncertain display_driver control!" severity warning;
      end if;
  end process ctrl;
  disp:process(display_time) is
  begin
    for i in display_time' range loop
       display(i)<=seven_seg(display_time(i));
    end loop;
  end process disp;
end behav;