alarm_clock.vhd

电子闹钟：基于fpga的电子闹钟设计

--整个设计中要用到的程序包定义程序p_alarm.vhd
library ieee;
use ieee.std_logic_1164.all;
package p_alarm is
  subtype t_digital is integer range 0 to 9;
  subtype t_short is integer range 0 to 65535;
  type t_clock_time is array(3 downto 0) of t_digital;
  type t_display is array(3 downto 0) of std_logic_vector(6 downto 0);
  type seg7 is array (0 to 9) of std_logic_vector(6 downto 0);
  constant seven_seg : seg7 := ( "1000000",  --0
                                 "1111001",  --1
                                 "0100100",  --2
                                 "0110000",  --3
                                 "0011001",  --4
                                 "0010010",  --5
                                 "0000010",  --6
                                 "1111000",  --7
                                 "0000000",  --8
                                 "0011000"  --9
                                );
end package p_alarm;
                                        

--整个闹钟系统的顶层文件alarm_clock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.p_alarm.all;
entity alarm_clock is
port( keypad : in std_logic_vector(9 downto 0);

      key_down : in std_logic;
      alarm_button: in std_logic;
      time_button : in std_logic;
      clk : in std_logic;
      reset : in std_logic;
      display : out t_display;
      sound_alarm : out std_logic);
end entity;
architecture behav of alarm_clock is
  component decoder is
  port( keypad : in std_logic_vector(9 downto 0);
        value : out t_digital);
  end component decoder;
  component key_buffer is
  port( key : in t_digital;
      clk : in std_logic;
      reset : in std_logic;
      new_time : out t_clock_time);
  end component;
  component alarm_controller is
  port( key : in std_logic;
      time_button : in std_logic;
      alarm_button : in std_logic;
      clk : in std_logic;
      reset : in std_logic;
      load_new_A : out std_logic;
      load_new_C : out std_logic;
      show_new_time : out std_logic;
      show_A : out std_logic);
  end component;
  component alarm_counter is
  port( new_current_time : in t_clock_time;
      load_new_C : in std_logic;
      clk : in std_logic;
      reset : in std_logic;
      current_time : out t_clock_time);
  end component;
  component alarm_reg is
  port( new_alarm_time : in t_clock_time;
      load_new_A : in std_logic;
      clk : in std_logic;
      reset : in std_logic;
      alarm_time : out t_clock_time);
  end component;
  component display_driver is
  port( alarm_time : in t_clock_time;
      current_time : in t_clock_time;
      new_time : in t_clock_time;
      show_new_time : in std_logic;
      show_A : in std_logic;
      sound_alarm : out std_logic;
      display : out t_display);
  end component;
  component fq_divider is
  port( clk_in : in std_logic;
      reset : in std_logic;
      clk_out : out std_logic);
  end component;
  
  
  signal s0 : t_digital;
  signal s1,s2,s3,s4,s5 : std_logic;
  signal s6,s7,s8 : t_clock_time;
begin
  u1: decoder port map (keypad,s0);
  u2: key_buffer port map (s0,key_down,reset,s6);
  u3: alarm_controller port map (key_down,time_button,alarm_button,clk,reset,s1,s2,s3,s4);
  u4: alarm_counter port map (s6,s2,s5,reset,s8);
  u5: alarm_reg port map (s6,s1,clk,reset,s7);
  u6: display_driver port map (s7,s8,s6,s3,s4,sound_alarm,display);
  u7: fq_divider port map (clk,reset,s5);
end behav;