alarm_reg.tan.qmsg

电子闹钟：基于fpga的电子闹钟设计

{ "Info" "ITDB_TSU_RESULT" "alarm_time\[2\]\[2\]~reg0 new_alarm_time\[2\]\[2\] clk 4.267 ns register " "Info: tsu for register \"alarm_time\[2\]\[2\]~reg0\" (data pin = \"new_alarm_time\[2\]\[2\]\", clock pin = \"clk\") is 4.267 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.956 ns + Longest pin register " "Info: + Longest pin to register delay is 6.956 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns new_alarm_time\[2\]\[2\] 1 PIN PIN_AC6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_AC6; Fanout = 1; PIN Node = 'new_alarm_time\[2\]\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { new_alarm_time[2][2] } "NODE_NAME" } } { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.740 ns) + CELL(0.366 ns) 6.956 ns alarm_time\[2\]\[2\]~reg0 2 REG LCFF_X1_Y25_N19 1 " "Info: 2: + IC(5.740 ns) + CELL(0.366 ns) = 6.956 ns; Loc. = LCFF_X1_Y25_N19; Fanout = 1; REG Node = 'alarm_time\[2\]\[2\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.106 ns" { new_alarm_time[2][2] alarm_time[2][2]~reg0 } "NODE_NAME" } } { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.216 ns ( 17.48 % ) " "Info: Total cell delay = 1.216 ns ( 17.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.740 ns ( 82.52 % ) " "Info: Total interconnect delay = 5.740 ns ( 82.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.956 ns" { new_alarm_time[2][2] alarm_time[2][2]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.956 ns" { new_alarm_time[2][2] new_alarm_time[2][2]~combout alarm_time[2][2]~reg0 } { 0.000ns 0.000ns 5.740ns } { 0.000ns 0.850ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.653 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.653 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.999 ns) + CELL(0.537 ns) 2.653 ns alarm_time\[2\]\[2\]~reg0 3 REG LCFF_X1_Y25_N19 1 " "Info: 3: + IC(0.999 ns) + CELL(0.537 ns) = 2.653 ns; Loc. = LCFF_X1_Y25_N19; Fanout = 1; REG Node = 'alarm_time\[2\]\[2\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.536 ns" { clk~clkctrl alarm_time[2][2]~reg0 } "NODE_NAME" } } { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.90 % ) " "Info: Total cell delay = 1.536 ns ( 57.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.117 ns ( 42.10 % ) " "Info: Total interconnect delay = 1.117 ns ( 42.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.653 ns" { clk clk~clkctrl alarm_time[2][2]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.653 ns" { clk clk~combout clk~clkctrl alarm_time[2][2]~reg0 } { 0.000ns 0.000ns 0.118ns 0.999ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.956 ns" { new_alarm_time[2][2] alarm_time[2][2]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.956 ns" { new_alarm_time[2][2] new_alarm_time[2][2]~combout alarm_time[2][2]~reg0 } { 0.000ns 0.000ns 5.740ns } { 0.000ns 0.850ns 0.366ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.653 ns" { clk clk~clkctrl alarm_time[2][2]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.653 ns" { clk clk~combout clk~clkctrl alarm_time[2][2]~reg0 } { 0.000ns 0.000ns 0.118ns 0.999ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk alarm_time\[1\]\[2\] alarm_time\[1\]\[2\]~reg0 6.795 ns register " "Info: tco from clock \"clk\" to destination pin \"alarm_time\[1\]\[2\]\" through register \"alarm_time\[1\]\[2\]~reg0\" is 6.795 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.653 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.653 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.999 ns) + CELL(0.537 ns) 2.653 ns alarm_time\[1\]\[2\]~reg0 3 REG LCFF_X1_Y25_N27 1 " "Info: 3: + IC(0.999 ns) + CELL(0.537 ns) = 2.653 ns; Loc. = LCFF_X1_Y25_N27; Fanout = 1; REG Node = 'alarm_time\[1\]\[2\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.536 ns" { clk~clkctrl alarm_time[1][2]~reg0 } "NODE_NAME" } } { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.90 % ) " "Info: Total cell delay = 1.536 ns ( 57.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.117 ns ( 42.10 % ) " "Info: Total interconnect delay = 1.117 ns ( 42.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.653 ns" { clk clk~clkctrl alarm_time[1][2]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.653 ns" { clk clk~combout clk~clkctrl alarm_time[1][2]~reg0 } { 0.000ns 0.000ns 0.118ns 0.999ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.892 ns + Longest register pin " "Info: + Longest register to pin delay is 3.892 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns alarm_time\[1\]\[2\]~reg0 1 REG LCFF_X1_Y25_N27 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y25_N27; Fanout = 1; REG Node = 'alarm_time\[1\]\[2\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { alarm_time[1][2]~reg0 } "NODE_NAME" } } { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.260 ns) + CELL(2.632 ns) 3.892 ns alarm_time\[1\]\[2\] 2 PIN PIN_P3 0 " "Info: 2: + IC(1.260 ns) + CELL(2.632 ns) = 3.892 ns; Loc. = PIN_P3; Fanout = 0; PIN Node = 'alarm_time\[1\]\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.892 ns" { alarm_time[1][2]~reg0 alarm_time[1][2] } "NODE_NAME" } } { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.632 ns ( 67.63 % ) " "Info: Total cell delay = 2.632 ns ( 67.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.260 ns ( 32.37 % ) " "Info: Total interconnect delay = 1.260 ns ( 32.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.892 ns" { alarm_time[1][2]~reg0 alarm_time[1][2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.892 ns" { alarm_time[1][2]~reg0 alarm_time[1][2] } { 0.000ns 1.260ns } { 0.000ns 2.632ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.653 ns" { clk clk~clkctrl alarm_time[1][2]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.653 ns" { clk clk~combout clk~clkctrl alarm_time[1][2]~reg0 } { 0.000ns 0.000ns 0.118ns 0.999ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.892 ns" { alarm_time[1][2]~reg0 alarm_time[1][2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.892 ns" { alarm_time[1][2]~reg0 alarm_time[1][2] } { 0.000ns 1.260ns } { 0.000ns 2.632ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "alarm_time\[0\]\[0\]~reg0 new_alarm_time\[0\]\[0\] clk -0.514 ns register " "Info: th for register \"alarm_time\[0\]\[0\]~reg0\" (data pin = \"new_alarm_time\[0\]\[0\]\", clock pin = \"clk\") is -0.514 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.653 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.653 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.999 ns) + CELL(0.537 ns) 2.653 ns alarm_time\[0\]\[0\]~reg0 3 REG LCFF_X1_Y25_N17 1 " "Info: 3: + IC(0.999 ns) + CELL(0.537 ns) = 2.653 ns; Loc. = LCFF_X1_Y25_N17; Fanout = 1; REG Node = 'alarm_time\[0\]\[0\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.536 ns" { clk~clkctrl alarm_time[0][0]~reg0 } "NODE_NAME" } } { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.90 % ) " "Info: Total cell delay = 1.536 ns ( 57.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.117 ns ( 42.10 % ) " "Info: Total interconnect delay = 1.117 ns ( 42.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.653 ns" { clk clk~clkctrl alarm_time[0][0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.653 ns" { clk clk~combout clk~clkctrl alarm_time[0][0]~reg0 } { 0.000ns 0.000ns 0.118ns 0.999ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.433 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.433 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns new_alarm_time\[0\]\[0\] 1 PIN PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; PIN Node = 'new_alarm_time\[0\]\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { new_alarm_time[0][0] } "NODE_NAME" } } { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.088 ns) + CELL(0.366 ns) 3.433 ns alarm_time\[0\]\[0\]~reg0 2 REG LCFF_X1_Y25_N17 1 " "Info: 2: + IC(2.088 ns) + CELL(0.366 ns) = 3.433 ns; Loc. = LCFF_X1_Y25_N17; Fanout = 1; REG Node = 'alarm_time\[0\]\[0\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.454 ns" { new_alarm_time[0][0] alarm_time[0][0]~reg0 } "NODE_NAME" } } { "alarm_reg.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/alarm_reg/alarm_reg.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.345 ns ( 39.18 % ) " "Info: Total cell delay = 1.345 ns ( 39.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.088 ns ( 60.82 % ) " "Info: Total interconnect delay = 2.088 ns ( 60.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.433 ns" { new_alarm_time[0][0] alarm_time[0][0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.433 ns" { new_alarm_time[0][0] new_alarm_time[0][0]~combout alarm_time[0][0]~reg0 } { 0.000ns 0.000ns 2.088ns } { 0.000ns 0.979ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.653 ns" { clk clk~clkctrl alarm_time[0][0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.653 ns" { clk clk~combout clk~clkctrl alarm_time[0][0]~reg0 } { 0.000ns 0.000ns 0.118ns 0.999ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.433 ns" { new_alarm_time[0][0] alarm_time[0][0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.433 ns" { new_alarm_time[0][0] new_alarm_time[0][0]~combout alarm_time[0][0]~reg0 } { 0.000ns 0.000ns 2.088ns } { 0.000ns 0.979ns 0.366ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 05 11:26:03 2008 " "Info: Processing ended: Sun Oct 05 11:26:03 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}