alarm_reg.tan.rpt

电子闹钟：基于fpga的电子闹钟设计

+-------------------------------------------------------------------------------------------+
; tco                                                                                       ;
+-------+--------------+------------+-----------------------+------------------+------------+
; Slack ; Required tco ; Actual tco ; From                  ; To               ; From Clock ;
+-------+--------------+------------+-----------------------+------------------+------------+
; N/A   ; None         ; 6.795 ns   ; alarm_time[1][2]~reg0 ; alarm_time[1][2] ; clk        ;
; N/A   ; None         ; 6.612 ns   ; alarm_time[2][3]~reg0 ; alarm_time[2][3] ; clk        ;
; N/A   ; None         ; 6.512 ns   ; alarm_time[1][0]~reg0 ; alarm_time[1][0] ; clk        ;
; N/A   ; None         ; 6.492 ns   ; alarm_time[3][0]~reg0 ; alarm_time[3][0] ; clk        ;
; N/A   ; None         ; 6.352 ns   ; alarm_time[0][3]~reg0 ; alarm_time[0][3] ; clk        ;
; N/A   ; None         ; 6.350 ns   ; alarm_time[2][2]~reg0 ; alarm_time[2][2] ; clk        ;
; N/A   ; None         ; 6.349 ns   ; alarm_time[3][1]~reg0 ; alarm_time[3][1] ; clk        ;
; N/A   ; None         ; 6.341 ns   ; alarm_time[2][1]~reg0 ; alarm_time[2][1] ; clk        ;
; N/A   ; None         ; 6.338 ns   ; alarm_time[3][3]~reg0 ; alarm_time[3][3] ; clk        ;
; N/A   ; None         ; 6.315 ns   ; alarm_time[1][3]~reg0 ; alarm_time[1][3] ; clk        ;
; N/A   ; None         ; 6.311 ns   ; alarm_time[0][2]~reg0 ; alarm_time[0][2] ; clk        ;
; N/A   ; None         ; 6.236 ns   ; alarm_time[0][0]~reg0 ; alarm_time[0][0] ; clk        ;
; N/A   ; None         ; 6.216 ns   ; alarm_time[3][2]~reg0 ; alarm_time[3][2] ; clk        ;
; N/A   ; None         ; 6.072 ns   ; alarm_time[1][1]~reg0 ; alarm_time[1][1] ; clk        ;
; N/A   ; None         ; 6.069 ns   ; alarm_time[2][0]~reg0 ; alarm_time[2][0] ; clk        ;
; N/A   ; None         ; 6.059 ns   ; alarm_time[0][1]~reg0 ; alarm_time[0][1] ; clk        ;
+-------+--------------+------------+-----------------------+------------------+------------+


+---------------------------------------------------------------------------------------------------+
; th                                                                                                ;
+---------------+-------------+-----------+----------------------+-----------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From                 ; To                    ; To Clock ;
+---------------+-------------+-----------+----------------------+-----------------------+----------+
; N/A           ; None        ; -0.514 ns ; new_alarm_time[0][0] ; alarm_time[0][0]~reg0 ; clk      ;
; N/A           ; None        ; -0.823 ns ; load_new_A           ; alarm_time[0][0]~reg0 ; clk      ;
; N/A           ; None        ; -0.823 ns ; load_new_A           ; alarm_time[0][1]~reg0 ; clk      ;
; N/A           ; None        ; -0.823 ns ; load_new_A           ; alarm_time[0][2]~reg0 ; clk      ;
; N/A           ; None        ; -0.823 ns ; load_new_A           ; alarm_time[0][3]~reg0 ; clk      ;
; N/A           ; None        ; -0.823 ns ; load_new_A           ; alarm_time[1][0]~reg0 ; clk      ;
; N/A           ; None        ; -0.823 ns ; load_new_A           ; alarm_time[1][1]~reg0 ; clk      ;
; N/A           ; None        ; -0.823 ns ; load_new_A           ; alarm_time[1][2]~reg0 ; clk      ;
; N/A           ; None        ; -0.823 ns ; load_new_A           ; alarm_time[1][3]~reg0 ; clk      ;
; N/A           ; None        ; -0.823 ns ; load_new_A           ; alarm_time[2][0]~reg0 ; clk      ;
; N/A           ; None        ; -0.823 ns ; load_new_A           ; alarm_time[2][1]~reg0 ; clk      ;
; N/A           ; None        ; -0.823 ns ; load_new_A           ; alarm_time[2][2]~reg0 ; clk      ;
; N/A           ; None        ; -0.823 ns ; load_new_A           ; alarm_time[2][3]~reg0 ; clk      ;
; N/A           ; None        ; -0.823 ns ; load_new_A           ; alarm_time[3][0]~reg0 ; clk      ;
; N/A           ; None        ; -0.823 ns ; load_new_A           ; alarm_time[3][1]~reg0 ; clk      ;
; N/A           ; None        ; -0.823 ns ; load_new_A           ; alarm_time[3][2]~reg0 ; clk      ;
; N/A           ; None        ; -0.823 ns ; load_new_A           ; alarm_time[3][3]~reg0 ; clk      ;
; N/A           ; None        ; -2.624 ns ; new_alarm_time[1][1] ; alarm_time[1][1]~reg0 ; clk      ;
; N/A           ; None        ; -2.641 ns ; new_alarm_time[1][0] ; alarm_time[1][0]~reg0 ; clk      ;
; N/A           ; None        ; -2.912 ns ; new_alarm_time[3][2] ; alarm_time[3][2]~reg0 ; clk      ;
; N/A           ; None        ; -2.945 ns ; new_alarm_time[3][0] ; alarm_time[3][0]~reg0 ; clk      ;
; N/A           ; None        ; -2.952 ns ; new_alarm_time[3][1] ; alarm_time[3][1]~reg0 ; clk      ;
; N/A           ; None        ; -3.050 ns ; new_alarm_time[1][3] ; alarm_time[1][3]~reg0 ; clk      ;
; N/A           ; None        ; -3.050 ns ; new_alarm_time[1][2] ; alarm_time[1][2]~reg0 ; clk      ;
; N/A           ; None        ; -3.063 ns ; new_alarm_time[3][3] ; alarm_time[3][3]~reg0 ; clk      ;
; N/A           ; None        ; -3.088 ns ; new_alarm_time[2][1] ; alarm_time[2][1]~reg0 ; clk      ;
; N/A           ; None        ; -3.150 ns ; new_alarm_time[0][3] ; alarm_time[0][3]~reg0 ; clk      ;
; N/A           ; None        ; -3.395 ns ; new_alarm_time[2][0] ; alarm_time[2][0]~reg0 ; clk      ;
; N/A           ; None        ; -3.450 ns ; new_alarm_time[2][3] ; alarm_time[2][3]~reg0 ; clk      ;
; N/A           ; None        ; -3.504 ns ; new_alarm_time[0][1] ; alarm_time[0][1]~reg0 ; clk      ;
; N/A           ; None        ; -3.521 ns ; new_alarm_time[0][2] ; alarm_time[0][2]~reg0 ; clk      ;
; N/A           ; None        ; -4.037 ns ; new_alarm_time[2][2] ; alarm_time[2][2]~reg0 ; clk      ;
+---------------+-------------+-----------+----------------------+-----------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Oct 05 11:26:02 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off alarm_reg -c alarm_reg --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clk"
Info: tsu for register "alarm_time[2][2]~reg0" (data pin = "new_alarm_time[2][2]", clock pin = "clk") is 4.267 ns
    Info: + Longest pin to register delay is 6.956 ns
        Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_AC6; Fanout = 1; PIN Node = 'new_alarm_time[2][2]'
        Info: 2: + IC(5.740 ns) + CELL(0.366 ns) = 6.956 ns; Loc. = LCFF_X1_Y25_N19; Fanout = 1; REG Node = 'alarm_time[2][2]~reg0'
        Info: Total cell delay = 1.216 ns ( 17.48 % )
        Info: Total interconnect delay = 5.740 ns ( 82.52 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.653 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.999 ns) + CELL(0.537 ns) = 2.653 ns; Loc. = LCFF_X1_Y25_N19; Fanout = 1; REG Node = 'alarm_time[2][2]~reg0'
        Info: Total cell delay = 1.536 ns ( 57.90 % )
        Info: Total interconnect delay = 1.117 ns ( 42.10 % )
Info: tco from clock "clk" to destination pin "alarm_time[1][2]" through register "alarm_time[1][2]~reg0" is 6.795 ns
    Info: + Longest clock path from clock "clk" to source register is 2.653 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.999 ns) + CELL(0.537 ns) = 2.653 ns; Loc. = LCFF_X1_Y25_N27; Fanout = 1; REG Node = 'alarm_time[1][2]~reg0'
        Info: Total cell delay = 1.536 ns ( 57.90 % )
        Info: Total interconnect delay = 1.117 ns ( 42.10 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.892 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y25_N27; Fanout = 1; REG Node = 'alarm_time[1][2]~reg0'
        Info: 2: + IC(1.260 ns) + CELL(2.632 ns) = 3.892 ns; Loc. = PIN_P3; Fanout = 0; PIN Node = 'alarm_time[1][2]'
        Info: Total cell delay = 2.632 ns ( 67.63 % )
        Info: Total interconnect delay = 1.260 ns ( 32.37 % )
Info: th for register "alarm_time[0][0]~reg0" (data pin = "new_alarm_time[0][0]", clock pin = "clk") is -0.514 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.653 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.999 ns) + CELL(0.537 ns) = 2.653 ns; Loc. = LCFF_X1_Y25_N17; Fanout = 1; REG Node = 'alarm_time[0][0]~reg0'
        Info: Total cell delay = 1.536 ns ( 57.90 % )
        Info: Total interconnect delay = 1.117 ns ( 42.10 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 3.433 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; PIN Node = 'new_alarm_time[0][0]'
        Info: 2: + IC(2.088 ns) + CELL(0.366 ns) = 3.433 ns; Loc. = LCFF_X1_Y25_N17; Fanout = 1; REG Node = 'alarm_time[0][0]~reg0'
        Info: Total cell delay = 1.345 ns ( 39.18 % )
        Info: Total interconnect delay = 2.088 ns ( 60.82 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Oct 05 11:26:03 2008
    Info: Elapsed time: 00:00:02