📄 alarm_reg.tan.rpt
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Timing Analyzer report for alarm_reg
Sun Oct 05 11:26:03 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. tsu
6. tco
7. th
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+-----------------------+-----------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-----------------------+-----------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 4.267 ns ; new_alarm_time[2][2] ; alarm_time[2][2]~reg0 ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 6.795 ns ; alarm_time[1][2]~reg0 ; alarm_time[1][2] ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -0.514 ns ; new_alarm_time[0][0] ; alarm_time[0][0]~reg0 ; -- ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+-----------------------+-----------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C35F672C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+---------------------------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+----------------------+-----------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+----------------------+-----------------------+----------+
; N/A ; None ; 4.267 ns ; new_alarm_time[2][2] ; alarm_time[2][2]~reg0 ; clk ;
; N/A ; None ; 3.751 ns ; new_alarm_time[0][2] ; alarm_time[0][2]~reg0 ; clk ;
; N/A ; None ; 3.734 ns ; new_alarm_time[0][1] ; alarm_time[0][1]~reg0 ; clk ;
; N/A ; None ; 3.680 ns ; new_alarm_time[2][3] ; alarm_time[2][3]~reg0 ; clk ;
; N/A ; None ; 3.625 ns ; new_alarm_time[2][0] ; alarm_time[2][0]~reg0 ; clk ;
; N/A ; None ; 3.380 ns ; new_alarm_time[0][3] ; alarm_time[0][3]~reg0 ; clk ;
; N/A ; None ; 3.318 ns ; new_alarm_time[2][1] ; alarm_time[2][1]~reg0 ; clk ;
; N/A ; None ; 3.293 ns ; new_alarm_time[3][3] ; alarm_time[3][3]~reg0 ; clk ;
; N/A ; None ; 3.280 ns ; new_alarm_time[1][3] ; alarm_time[1][3]~reg0 ; clk ;
; N/A ; None ; 3.280 ns ; new_alarm_time[1][2] ; alarm_time[1][2]~reg0 ; clk ;
; N/A ; None ; 3.182 ns ; new_alarm_time[3][1] ; alarm_time[3][1]~reg0 ; clk ;
; N/A ; None ; 3.175 ns ; new_alarm_time[3][0] ; alarm_time[3][0]~reg0 ; clk ;
; N/A ; None ; 3.142 ns ; new_alarm_time[3][2] ; alarm_time[3][2]~reg0 ; clk ;
; N/A ; None ; 2.871 ns ; new_alarm_time[1][0] ; alarm_time[1][0]~reg0 ; clk ;
; N/A ; None ; 2.854 ns ; new_alarm_time[1][1] ; alarm_time[1][1]~reg0 ; clk ;
; N/A ; None ; 1.053 ns ; load_new_A ; alarm_time[0][0]~reg0 ; clk ;
; N/A ; None ; 1.053 ns ; load_new_A ; alarm_time[0][1]~reg0 ; clk ;
; N/A ; None ; 1.053 ns ; load_new_A ; alarm_time[0][2]~reg0 ; clk ;
; N/A ; None ; 1.053 ns ; load_new_A ; alarm_time[0][3]~reg0 ; clk ;
; N/A ; None ; 1.053 ns ; load_new_A ; alarm_time[1][0]~reg0 ; clk ;
; N/A ; None ; 1.053 ns ; load_new_A ; alarm_time[1][1]~reg0 ; clk ;
; N/A ; None ; 1.053 ns ; load_new_A ; alarm_time[1][2]~reg0 ; clk ;
; N/A ; None ; 1.053 ns ; load_new_A ; alarm_time[1][3]~reg0 ; clk ;
; N/A ; None ; 1.053 ns ; load_new_A ; alarm_time[2][0]~reg0 ; clk ;
; N/A ; None ; 1.053 ns ; load_new_A ; alarm_time[2][1]~reg0 ; clk ;
; N/A ; None ; 1.053 ns ; load_new_A ; alarm_time[2][2]~reg0 ; clk ;
; N/A ; None ; 1.053 ns ; load_new_A ; alarm_time[2][3]~reg0 ; clk ;
; N/A ; None ; 1.053 ns ; load_new_A ; alarm_time[3][0]~reg0 ; clk ;
; N/A ; None ; 1.053 ns ; load_new_A ; alarm_time[3][1]~reg0 ; clk ;
; N/A ; None ; 1.053 ns ; load_new_A ; alarm_time[3][2]~reg0 ; clk ;
; N/A ; None ; 1.053 ns ; load_new_A ; alarm_time[3][3]~reg0 ; clk ;
; N/A ; None ; 0.744 ns ; new_alarm_time[0][0] ; alarm_time[0][0]~reg0 ; clk ;
+-------+--------------+------------+----------------------+-----------------------+----------+
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