alarm_reg.vhd

来自「电子闹钟：基于fpga的电子闹钟设计」· VHDL 代码 · 共 31 行

                                        

--闹钟寄存器的源程序alarm_reg.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
entity alarm_reg is
port( new_alarm_time : in t_clock_time;
      load_new_A : in std_logic;
      clk : in std_logic;
      reset : in std_logic;
      alarm_time : out t_clock_time);
end entity;
architecture behav of alarm_reg is
begin
  process(clk,reset)
  begin
    if reset='1' then
      alarm_time<=(0,0,0,0);
    else
      if rising_edge(clk) then
        if load_new_A='1' then
          alarm_time<=new_alarm_time;
        else 
          assert false report "Uncertain load_new_alarm control!"  severity warning;
        end if;
      end if;
    end if;
  end process;
end behav;