mapy.tan.qmsg

可以用于按键去抖动的电路应用

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register pre_s.s0 pre_s.s1 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"pre_s.s0\" and destination register \"pre_s.s1\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.665 ns + Longest register register " "Info: + Longest register to register delay is 0.665 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pre_s.s0 1 REG LCFF_X30_Y35_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y35_N9; Fanout = 2; REG Node = 'pre_s.s0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pre_s.s0 } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.306 ns) + CELL(0.275 ns) 0.581 ns Selector1~12 2 COMB LCCOMB_X30_Y35_N0 1 " "Info: 2: + IC(0.306 ns) + CELL(0.275 ns) = 0.581 ns; Loc. = LCCOMB_X30_Y35_N0; Fanout = 1; COMB Node = 'Selector1~12'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.581 ns" { pre_s.s0 Selector1~12 } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.665 ns pre_s.s1 3 REG LCFF_X30_Y35_N1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.665 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 1; REG Node = 'pre_s.s1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Selector1~12 pre_s.s1 } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.359 ns ( 53.98 % ) " "Info: Total cell delay = 0.359 ns ( 53.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.306 ns ( 46.02 % ) " "Info: Total interconnect delay = 0.306 ns ( 46.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.665 ns" { pre_s.s0 Selector1~12 pre_s.s1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.665 ns" { pre_s.s0 Selector1~12 pre_s.s1 } { 0.000ns 0.306ns 0.000ns } { 0.000ns 0.275ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.698 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.537 ns) 2.698 ns pre_s.s1 3 REG LCFF_X30_Y35_N1 1 " "Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 1; REG Node = 'pre_s.s1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.581 ns" { clk~clkctrl pre_s.s1 } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.93 % ) " "Info: Total cell delay = 1.536 ns ( 56.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 43.07 % ) " "Info: Total interconnect delay = 1.162 ns ( 43.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl pre_s.s1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl pre_s.s1 } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.698 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.537 ns) 2.698 ns pre_s.s0 3 REG LCFF_X30_Y35_N9 2 " "Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X30_Y35_N9; Fanout = 2; REG Node = 'pre_s.s0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.581 ns" { clk~clkctrl pre_s.s0 } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.93 % ) " "Info: Total cell delay = 1.536 ns ( 56.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 43.07 % ) " "Info: Total interconnect delay = 1.162 ns ( 43.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl pre_s.s0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl pre_s.s0 } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl pre_s.s1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl pre_s.s1 } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl pre_s.s0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl pre_s.s0 } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.665 ns" { pre_s.s0 Selector1~12 pre_s.s1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.665 ns" { pre_s.s0 Selector1~12 pre_s.s1 } { 0.000ns 0.306ns 0.000ns } { 0.000ns 0.275ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl pre_s.s1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl pre_s.s1 } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl pre_s.s0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl pre_s.s0 } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pre_s.s1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { pre_s.s1 } {  } {  } } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "pre_s.s1 din clk -0.583 ns register " "Info: tsu for register \"pre_s.s1\" (data pin = \"din\", clock pin = \"clk\") is -0.583 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.151 ns + Longest pin register " "Info: + Longest pin to register delay is 2.151 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns din 1 PIN PIN_C13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 4; PIN Node = 'din'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { din } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.668 ns) + CELL(0.420 ns) 2.067 ns Selector1~12 2 COMB LCCOMB_X30_Y35_N0 1 " "Info: 2: + IC(0.668 ns) + CELL(0.420 ns) = 2.067 ns; Loc. = LCCOMB_X30_Y35_N0; Fanout = 1; COMB Node = 'Selector1~12'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.088 ns" { din Selector1~12 } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.151 ns pre_s.s1 3 REG LCFF_X30_Y35_N1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.151 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 1; REG Node = 'pre_s.s1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Selector1~12 pre_s.s1 } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.483 ns ( 68.94 % ) " "Info: Total cell delay = 1.483 ns ( 68.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.668 ns ( 31.06 % ) " "Info: Total interconnect delay = 0.668 ns ( 31.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.151 ns" { din Selector1~12 pre_s.s1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.151 ns" { din din~combout Selector1~12 pre_s.s1 } { 0.000ns 0.000ns 0.668ns 0.000ns } { 0.000ns 0.979ns 0.420ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.698 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.537 ns) 2.698 ns pre_s.s1 3 REG LCFF_X30_Y35_N1 1 " "Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 1; REG Node = 'pre_s.s1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.581 ns" { clk~clkctrl pre_s.s1 } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.93 % ) " "Info: Total cell delay = 1.536 ns ( 56.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 43.07 % ) " "Info: Total interconnect delay = 1.162 ns ( 43.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl pre_s.s1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl pre_s.s1 } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.151 ns" { din Selector1~12 pre_s.s1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.151 ns" { din din~combout Selector1~12 pre_s.s1 } { 0.000ns 0.000ns 0.668ns 0.000ns } { 0.000ns 0.979ns 0.420ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl pre_s.s1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl pre_s.s1 } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout pre_s.s3 6.368 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\" through register \"pre_s.s3\" is 6.368 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.698 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.537 ns) 2.698 ns pre_s.s3 3 REG LCFF_X30_Y35_N23 2 " "Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X30_Y35_N23; Fanout = 2; REG Node = 'pre_s.s3'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.581 ns" { clk~clkctrl pre_s.s3 } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.93 % ) " "Info: Total cell delay = 1.536 ns ( 56.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 43.07 % ) " "Info: Total interconnect delay = 1.162 ns ( 43.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl pre_s.s3 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl pre_s.s3 } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.420 ns + Longest register pin " "Info: + Longest register to pin delay is 3.420 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pre_s.s3 1 REG LCFF_X30_Y35_N23 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y35_N23; Fanout = 2; REG Node = 'pre_s.s3'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pre_s.s3 } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.632 ns) + CELL(2.788 ns) 3.420 ns dout 2 PIN PIN_C12 0 " "Info: 2: + IC(0.632 ns) + CELL(2.788 ns) = 3.420 ns; Loc. = PIN_C12; Fanout = 0; PIN Node = 'dout'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.420 ns" { pre_s.s3 dout } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.788 ns ( 81.52 % ) " "Info: Total cell delay = 2.788 ns ( 81.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.632 ns ( 18.48 % ) " "Info: Total interconnect delay = 0.632 ns ( 18.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.420 ns" { pre_s.s3 dout } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.420 ns" { pre_s.s3 dout } { 0.000ns 0.632ns } { 0.000ns 2.788ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl pre_s.s3 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl pre_s.s3 } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.420 ns" { pre_s.s3 dout } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.420 ns" { pre_s.s3 dout } { 0.000ns 0.632ns } { 0.000ns 2.788ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "pre_s.s0 din clk 1.087 ns register " "Info: th for register \"pre_s.s0\" (data pin = \"din\", clock pin = \"clk\") is 1.087 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.698 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.537 ns) 2.698 ns pre_s.s0 3 REG LCFF_X30_Y35_N9 2 " "Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X30_Y35_N9; Fanout = 2; REG Node = 'pre_s.s0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.581 ns" { clk~clkctrl pre_s.s0 } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.93 % ) " "Info: Total cell delay = 1.536 ns ( 56.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 43.07 % ) " "Info: Total interconnect delay = 1.162 ns ( 43.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl pre_s.s0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl pre_s.s0 } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.877 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.877 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns din 1 PIN PIN_C13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 4; PIN Node = 'din'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { din } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.664 ns) + CELL(0.150 ns) 1.793 ns pre_s.s0~8 2 COMB LCCOMB_X30_Y35_N8 1 " "Info: 2: + IC(0.664 ns) + CELL(0.150 ns) = 1.793 ns; Loc. = LCCOMB_X30_Y35_N8; Fanout = 1; COMB Node = 'pre_s.s0~8'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.814 ns" { din pre_s.s0~8 } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.877 ns pre_s.s0 3 REG LCFF_X30_Y35_N9 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 1.877 ns; Loc. = LCFF_X30_Y35_N9; Fanout = 2; REG Node = 'pre_s.s0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { pre_s.s0~8 pre_s.s0 } "NODE_NAME" } } { "mapy.vhd" "" { Text "E:/SOPClab/digital_system_design/an_jian_qu_dou_dong/mapy.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.213 ns ( 64.62 % ) " "Info: Total cell delay = 1.213 ns ( 64.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.664 ns ( 35.38 % ) " "Info: Total interconnect delay = 0.664 ns ( 35.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.877 ns" { din pre_s.s0~8 pre_s.s0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.877 ns" { din din~combout pre_s.s0~8 pre_s.s0 } { 0.000ns 0.000ns 0.664ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl pre_s.s0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl pre_s.s0 } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.877 ns" { din pre_s.s0~8 pre_s.s0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.877 ns" { din din~combout pre_s.s0~8 pre_s.s0 } { 0.000ns 0.000ns 0.664ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}