prev_cmp_dds.tan.qmsg

来自「基于DDS原理的正弦信号发生器。用VERILOG语言实现」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WTDB_CLOCK_REQ_RESTRICTED" "altpll0:inst1\|altpll:altpll_component\|_clk0 5.554 ns " "Warning: Clock period specified in clock requirement for clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" must be greater than or equal to the I/O edge rate limit of 5.554 ns in the currently selected device" {  } { { "altpll.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "Clock period specified in clock requirement for clock \"%1!s!\" must be greater than or equal to the I/O edge rate limit of %2!s! in the currently selected device" 0 0 "" 0}