dds.fit.rpt

基于DDS原理的正弦信号发生器。用VERILOG语言实现

Fitter report for DDS
Mon Jul 28 11:06:11 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. PLL Summary
 11. PLL Usage
 12. Output Pin Default Load For Reported TCO
 13. Fitter Resource Utilization by Entity
 14. Delay Chain Summary
 15. Pad To Core Delay Chain Fanout
 16. Control Signals
 17. Global & Other Fast Signals
 18. Non-Global High Fan-Out Signals
 19. Fitter RAM Summary
 20. Interconnect Usage Summary
 21. LAB Logic Elements
 22. LAB-wide Signals
 23. LAB Signals Sourced
 24. LAB Signals Sourced Out
 25. LAB Distinct Inputs
 26. Fitter Device Options
 27. Operating Settings and Conditions
 28. Fitter Messages
 29. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Fitter Summary                                                                ;
+------------------------------------+------------------------------------------+
; Fitter Status                      ; Successful - Mon Jul 28 11:06:11 2008    ;
; Quartus II Version                 ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name                      ; DDS                                      ;
; Top-level Entity Name              ; DDDS                                     ;
; Family                             ; Cyclone II                               ;
; Device                             ; EP2C35U484C8                             ;
; Timing Models                      ; Final                                    ;
; Total logic elements               ; 31 / 33,216 ( < 1 % )                    ;
;     Total combinational functions  ; 31 / 33,216 ( < 1 % )                    ;
;     Dedicated logic registers      ; 21 / 33,216 ( < 1 % )                    ;
; Total registers                    ; 21                                       ;
; Total pins                         ; 35 / 322 ( 11 % )                        ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 10,240 / 483,840 ( 2 % )                 ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                           ;
; Total PLLs                         ; 1 / 4 ( 25 % )                           ;
+------------------------------------+------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; EP2C35U484C8                   ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                   ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                         ; Off                            ; Off                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;