dds.tan.rpt

来自「基于DDS原理的正弦信号发生器。用VERILOG语言实现」· RPT 代码 · 共 227 行 · 第 1/5 页

; Worst-case tco                                             ; N/A      ; None                             ; 11.550 ns                        ; DDS:inst|rom0:rom0_instant|altsyncram:Ram0_rtl_0|altsyncram_4m71:auto_generated|ram_block1a0~porta_address_reg9 ; sinout[0]        ; clk                                         ; --                                          ; 0            ;
; Worst-case th                                              ; N/A      ; None                             ; -6.875 ns                        ; freqword[0]                                                                                                     ; DDS:inst|add[0]  ; --                                          ; clk                                         ; 0            ;
; Clock Setup: 'altpll0:inst1|altpll:altpll_component|_clk0' ; 2.877 ns ; 150.02 MHz ( period = 6.666 ns ) ; 263.92 MHz ( period = 3.789 ns ) ; DDS:inst|add[0]                                                                                                 ; DDS:inst|add[19] ; altpll0:inst1|altpll:altpll_component|_clk0 ; altpll0:inst1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'altpll0:inst1|altpll:altpll_component|_clk0'  ; 1.148 ns ; 150.02 MHz ( period = 6.666 ns ) ; N/A                              ; DDS:inst|add[1]                                                                                                 ; DDS:inst|add[1]  ; altpll0:inst1|altpll:altpll_component|_clk0 ; altpll0:inst1|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                               ;          ;                                  ;                                  ;                                                                                                                 ;                  ;                                             ;                                             ; 0            ;
+------------------------------------------------------------+----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------+---------------------------------------------+---------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP2C35U484C8       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                              ;
+---------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                             ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+---------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; altpll0:inst1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 150.02 MHz       ; 0.000 ns      ; 0.000 ns     ; clk      ; 3                     ; 1                   ; -2.804 ns ;              ;
; clk                                         ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+---------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+