we.map.eqn

出血FPGA,用VHDL做的音乐盒

-- Copyright (C) 1991-2006 Altera Corporation
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-- without limitation, that your use is for the sole purpose of 
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--G1_q_a[3] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 4
--Port A Input: Registered, Port A Output: Registered
G1_q_a[3]_PORT_A_address = BUS(E1_Counter[0], E1_Counter[1], E1_Counter[2], E1_Counter[3], E1_Counter[4], E1_Counter[5], E1_Counter[6], E1_Counter[7]);
G1_q_a[3]_PORT_A_address_reg = DFFE(G1_q_a[3]_PORT_A_address, G1_q_a[3]_clock_0, , , );
G1_q_a[3]_clock_0 = CLK8Hz;
G1_q_a[3]_PORT_A_data_out = MEMORY(, , G1_q_a[3]_PORT_A_address_reg, , , , , , G1_q_a[3]_clock_0, , , , , );
G1_q_a[3]_PORT_A_data_out_reg = DFFE(G1_q_a[3]_PORT_A_data_out, G1_q_a[3]_clock_0, , , );
G1_q_a[3] = G1_q_a[3]_PORT_A_data_out_reg[0];


--G1_q_a[0] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 4
--Port A Input: Registered, Port A Output: Registered
G1_q_a[0]_PORT_A_address = BUS(E1_Counter[0], E1_Counter[1], E1_Counter[2], E1_Counter[3], E1_Counter[4], E1_Counter[5], E1_Counter[6], E1_Counter[7]);
G1_q_a[0]_PORT_A_address_reg = DFFE(G1_q_a[0]_PORT_A_address, G1_q_a[0]_clock_0, , , );
G1_q_a[0]_clock_0 = CLK8Hz;
G1_q_a[0]_PORT_A_data_out = MEMORY(, , G1_q_a[0]_PORT_A_address_reg, , , , , , G1_q_a[0]_clock_0, , , , , );
G1_q_a[0]_PORT_A_data_out_reg = DFFE(G1_q_a[0]_PORT_A_data_out, G1_q_a[0]_clock_0, , , );
G1_q_a[0] = G1_q_a[0]_PORT_A_data_out_reg[0];


--G1_q_a[1] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 4
--Port A Input: Registered, Port A Output: Registered
G1_q_a[1]_PORT_A_address = BUS(E1_Counter[0], E1_Counter[1], E1_Counter[2], E1_Counter[3], E1_Counter[4], E1_Counter[5], E1_Counter[6], E1_Counter[7]);
G1_q_a[1]_PORT_A_address_reg = DFFE(G1_q_a[1]_PORT_A_address, G1_q_a[1]_clock_0, , , );
G1_q_a[1]_clock_0 = CLK8Hz;
G1_q_a[1]_PORT_A_data_out = MEMORY(, , G1_q_a[1]_PORT_A_address_reg, , , , , , G1_q_a[1]_clock_0, , , , , );
G1_q_a[1]_PORT_A_data_out_reg = DFFE(G1_q_a[1]_PORT_A_data_out, G1_q_a[1]_clock_0, , , );
G1_q_a[1] = G1_q_a[1]_PORT_A_data_out_reg[0];


--G1_q_a[2] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 4
--Port A Input: Registered, Port A Output: Registered
G1_q_a[2]_PORT_A_address = BUS(E1_Counter[0], E1_Counter[1], E1_Counter[2], E1_Counter[3], E1_Counter[4], E1_Counter[5], E1_Counter[6], E1_Counter[7]);
G1_q_a[2]_PORT_A_address_reg = DFFE(G1_q_a[2]_PORT_A_address, G1_q_a[2]_clock_0, , , );
G1_q_a[2]_clock_0 = CLK8Hz;
G1_q_a[2]_PORT_A_data_out = MEMORY(, , G1_q_a[2]_PORT_A_address_reg, , , , , , G1_q_a[2]_clock_0, , , , , );
G1_q_a[2]_PORT_A_data_out_reg = DFFE(G1_q_a[2]_PORT_A_data_out, G1_q_a[2]_clock_0, , , );
G1_q_a[2] = G1_q_a[2]_PORT_A_data_out_reg[0];


--D1L9 is TONETABA:inst2|Mux4~31
--operation mode is normal

D1L9 = G1_q_a[0] & G1_q_a[1] & !G1_q_a[2] & G1_q_a[3] # !G1_q_a[0] & G1_q_a[2] & (G1_q_a[1] $ !G1_q_a[3]);


--D1L8 is TONETABA:inst2|Mux3~21
--operation mode is normal

D1L8 = G1_q_a[3] & G1_q_a[1] # !G1_q_a[2];


--D1L7 is TONETABA:inst2|Mux2~33
--operation mode is normal

D1L7 = G1_q_a[1] $ (G1_q_a[3] & G1_q_a[0]);


--D1L6 is TONETABA:inst2|Mux1~79
--operation mode is normal

D1L6 = G1_q_a[3] & (G1_q_a[1] # !G1_q_a[0]) # !G1_q_a[3] & (G1_q_a[0]);


--E1_Counter[0] is NoteTabs:inst3|Counter[0]
--operation mode is normal

E1_Counter[0]_lut_out = !E1_Counter[0];
E1_Counter[0] = DFFEAS(E1_Counter[0]_lut_out, CLK8Hz, !E1L18, , , , , , );


--E1_Counter[1] is NoteTabs:inst3|Counter[1]
--operation mode is arithmetic

E1_Counter[1]_lut_out = E1_Counter[1] $ E1_Counter[0];
E1_Counter[1] = DFFEAS(E1_Counter[1]_lut_out, CLK8Hz, !E1L18, , , , , , );

--E1L4 is NoteTabs:inst3|Counter[1]~30
--operation mode is arithmetic

E1L4 = CARRY(E1_Counter[1] & E1_Counter[0]);


--E1_Counter[2] is NoteTabs:inst3|Counter[2]
--operation mode is arithmetic

E1_Counter[2]_carry_eqn = E1L4;
E1_Counter[2]_lut_out = E1_Counter[2] $ (E1_Counter[2]_carry_eqn);
E1_Counter[2] = DFFEAS(E1_Counter[2]_lut_out, CLK8Hz, !E1L18, , , , , , );

--E1L6 is NoteTabs:inst3|Counter[2]~31
--operation mode is arithmetic

E1L6 = CARRY(!E1L4 # !E1_Counter[2]);


--E1_Counter[3] is NoteTabs:inst3|Counter[3]
--operation mode is arithmetic

E1_Counter[3]_carry_eqn = E1L6;
E1_Counter[3]_lut_out = E1_Counter[3] $ (!E1_Counter[3]_carry_eqn);
E1_Counter[3] = DFFEAS(E1_Counter[3]_lut_out, CLK8Hz, !E1L18, , , , , , );

--E1L8 is NoteTabs:inst3|Counter[3]~32
--operation mode is arithmetic

E1L8 = CARRY(E1_Counter[3] & (!E1L6));


--E1_Counter[4] is NoteTabs:inst3|Counter[4]
--operation mode is arithmetic

E1_Counter[4]_carry_eqn = E1L8;
E1_Counter[4]_lut_out = E1_Counter[4] $ (E1_Counter[4]_carry_eqn);
E1_Counter[4] = DFFEAS(E1_Counter[4]_lut_out, CLK8Hz, !E1L18, , , , , , );

--E1L10 is NoteTabs:inst3|Counter[4]~33
--operation mode is arithmetic

E1L10 = CARRY(!E1L8 # !E1_Counter[4]);


--E1_Counter[5] is NoteTabs:inst3|Counter[5]
--operation mode is arithmetic

E1_Counter[5]_carry_eqn = E1L10;
E1_Counter[5]_lut_out = E1_Counter[5] $ (!E1_Counter[5]_carry_eqn);
E1_Counter[5] = DFFEAS(E1_Counter[5]_lut_out, CLK8Hz, !E1L18, , , , , , );

--E1L12 is NoteTabs:inst3|Counter[5]~34
--operation mode is arithmetic

E1L12 = CARRY(E1_Counter[5] & (!E1L10));


--E1_Counter[6] is NoteTabs:inst3|Counter[6]
--operation mode is arithmetic

E1_Counter[6]_carry_eqn = E1L12;
E1_Counter[6]_lut_out = E1_Counter[6] $ (E1_Counter[6]_carry_eqn);
E1_Counter[6] = DFFEAS(E1_Counter[6]_lut_out, CLK8Hz, !E1L18, , , , , , );

--E1L14 is NoteTabs:inst3|Counter[6]~35
--operation mode is arithmetic

E1L14 = CARRY(!E1L12 # !E1_Counter[6]);


--E1_Counter[7] is NoteTabs:inst3|Counter[7]
--operation mode is normal

E1_Counter[7]_carry_eqn = E1L14;
E1_Counter[7]_lut_out = E1_Counter[7] $ (!E1_Counter[7]_carry_eqn);
E1_Counter[7] = DFFEAS(E1_Counter[7]_lut_out, CLK8Hz, !E1L18, , , , , , );


--E1L16 is NoteTabs:inst3|Equal0~66
--operation mode is normal

E1L16 = E1_Counter[1] & (!E1_Counter[0]);


--E1L17 is NoteTabs:inst3|Equal0~67
--operation mode is normal

E1L17 = E1_Counter[7] & !E1_Counter[4] & !E1_Counter[5] & !E1_Counter[6];


--E1L18 is NoteTabs:inst3|Equal0~68
--operation mode is normal

E1L18 = E1_Counter[3] & E1L16 & E1L17 & !E1_Counter[2];


--D1_HIGH is TONETABA:inst2|HIGH
--operation mode is normal

D1_HIGH = D1L9 & (D1_HIGH) # !D1L9 & G1_q_a[3];


--D1_CODE[2] is TONETABA:inst2|CODE[2]
--operation mode is normal

D1_CODE[2] = D1L9 & (D1_CODE[2]) # !D1L9 & !D1L8;


--D1_CODE[1] is TONETABA:inst2|CODE[1]
--operation mode is normal

D1_CODE[1] = D1L9 & (D1_CODE[1]) # !D1L9 & D1L7;


--D1_CODE[0] is TONETABA:inst2|CODE[0]
--operation mode is normal

D1_CODE[0] = D1L9 & (D1_CODE[0]) # !D1L9 & D1L6;


--CLK12M is CLK12M
--operation mode is input

CLK12M = INPUT();


--CLK8Hz is CLK8Hz
--operation mode is input

CLK8Hz = INPUT();


--HIGN is HIGN
--operation mode is output

HIGN = OUTPUT(D1_HIGH);


--SPKS is SPKS
--operation mode is output

SPKS = OUTPUT(GND);


--CODE[3] is CODE[3]
--operation mode is output

CODE[3] = OUTPUT(GND);


--CODE[2] is CODE[2]
--operation mode is output

CODE[2] = OUTPUT(D1_CODE[2]);


--CODE[1] is CODE[1]
--operation mode is output

CODE[1] = OUTPUT(D1_CODE[1]);


--CODE[0] is CODE[0]
--operation mode is output

CODE[0] = OUTPUT(D1_CODE[0]);