we.map.summary

出血FPGA,用VHDL做的音乐盒

Analysis & Synthesis Status : Successful - Tue Sep 23 20:21:51 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : we
Top-level Entity Name : we
Family : Stratix
Total logic elements : 19
Total pins : 8
Total virtual pins : 0
Total memory bits : 1,024
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0