📄 we.fit.rpt
字号:
Fitter report for we
Tue Sep 23 20:21:59 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Equations
5. Pin-Out File
6. Fitter Resource Usage Summary
7. Input Pins
8. Output Pins
9. I/O Bank Usage
10. All Package Pins
11. Output Pin Default Load For Reported TCO
12. Fitter Resource Utilization by Entity
13. Delay Chain Summary
14. Pad To Core Delay Chain Fanout
15. Control Signals
16. Global & Other Fast Signals
17. Non-Global High Fan-Out Signals
18. Fitter RAM Summary
19. Interconnect Usage Summary
20. LAB Logic Elements
21. LAB-wide Signals
22. LAB Signals Sourced
23. LAB Signals Sourced Out
24. LAB Distinct Inputs
25. Fitter Device Options
26. Advanced Data - General
27. Advanced Data - Placement Preparation
28. Advanced Data - Placement
29. Advanced Data - Routing
30. Fitter Messages
31. Fitter Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------+
; Fitter Summary ;
+--------------------------+------------------------------------------+
; Fitter Status ; Successful - Tue Sep 23 20:21:59 2008 ;
; Quartus II Version ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name ; we ;
; Top-level Entity Name ; we ;
; Family ; Stratix ;
; Device ; EP1S10F484C5 ;
; Timing Models ; Final ;
; Total logic elements ; 20 / 10,570 ( < 1 % ) ;
; Total pins ; 8 / 336 ( 2 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,024 / 920,448 ( < 1 % ) ;
; DSP block 9-bit elements ; 0 / 48 ( 0 % ) ;
; Total PLLs ; 0 / 6 ( 0 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
+--------------------------+------------------------------------------+
+--------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------------------------------+
Option : Device
Setting : AUTO
Default Value :
Option : Use smart compilation
Setting : Off
Default Value : Off
Option : Router Timing Optimization Level
Setting : Normal
Default Value : Normal
Option : Placement Effort Multiplier
Setting : 1.0
Default Value : 1.0
Option : Router Effort Multiplier
Setting : 1.0
Default Value : 1.0
Option : Optimize Hold Timing
Setting : IO Paths and Minimum TPD Paths
Default Value : IO Paths and Minimum TPD Paths
Option : Optimize Fast-Corner Timing
Setting : Off
Default Value : Off
Option : Optimize Timing
Setting : Normal compilation
Default Value : Normal compilation
Option : Optimize IOC Register Placement for Timing
Setting : On
Default Value : On
Option : Limit to One Fitting Attempt
Setting : Off
Default Value : Off
Option : Final Placement Optimizations
Setting : Automatically
Default Value : Automatically
Option : Fitter Aggressive Routability Optimizations
Setting : Automatically
Default Value : Automatically
Option : Fitter Initial Placement Seed
Setting : 1
Default Value : 1
Option : Slow Slew Rate
Setting : Off
Default Value : Off
Option : PCI I/O
Setting : Off
Default Value : Off
Option : Weak Pull-Up Resistor
Setting : Off
Default Value : Off
Option : Enable Bus-Hold Circuitry
Setting : Off
Default Value : Off
Option : Auto Global Memory Control Signals
Setting : Off
Default Value : Off
Option : Auto Packed Registers -- Stratix/Stratix GX
Setting : Auto
Default Value : Auto
Option : Auto Delay Chains
Setting : On
Default Value : On
Option : Auto Merge PLLs
Setting : On
Default Value : On
Option : Perform Physical Synthesis for Combinational Logic
Setting : Off
Default Value : Off
Option : Perform Register Duplication
Setting : Off
Default Value : Off
Option : Perform Register Retiming
Setting : Off
Default Value : Off
Option : Perform Asynchronous Signal Pipelining
Setting : Off
Default Value : Off
Option : Fitter Effort
Setting : Auto Fit
Default Value : Auto Fit
Option : Physical Synthesis Effort Level
Setting : Normal
Default Value : Normal
Option : Logic Cell Insertion - Logic Duplication
Setting : Auto
Default Value : Auto
Option : Auto Register Duplication
Setting : Auto
Default Value : Auto
Option : Auto Global Clock
Setting : On
Default Value : On
Option : Auto Global Register Control Signals
Setting : On
Default Value : On
+--------------------------------------------------------------------------------+
+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in D:/PLD/FPGAlicheng/music/we.fit.eqn.
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/PLD/FPGAlicheng/music/we.pin.
+-----------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+-------------------------------------------------------------------------------------+
; Resource ; Usage ;
+---------------------------------------------+-------------------------------------------------------------------------------------+
; Total logic elements ; 20 / 10,570 ( < 1 % ) ;
; -- Combinational with no register ; 12 ;
; -- Register only ; 0 ;
; -- Combinational with a register ; 8 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 3 ;
; -- 3 input functions ; 7 ;
; -- 2 input functions ; 8 ;
; -- 1 input functions ; 1 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 14 ;
; -- arithmetic mode ; 6 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 8 ;
; ; ;
; Total LABs ; 4 / 1,057 ( < 1 % ) ;
; Logic elements in carry chains ; 7 ;
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 8 / 336 ( 2 % ) ;
; -- Clock pins ; 1 / 16 ( 6 % ) ;
; Global signals ; 3 ;
; M512s ; 0 / 94 ( 0 % ) ;
; M4Ks ; 1 / 60 ( 2 % ) ;
; M-RAMs ; 0 / 1 ( 0 % ) ;
; Total memory bits ; 1,024 / 920,448 ( < 1 % ) ;
; Total RAM block bits ; 4,608 / 920,448 ( < 1 % ) ;
; DSP block 9-bit elements ; 0 / 48 ( 0 % ) ;
; PLLs ; 0 / 6 ( 0 % ) ;
; Global clocks ; 3 / 16 ( 19 % ) ;
; Regional clocks ; 0 / 16 ( 0 % ) ;
; Fast regional clocks ; 0 / 8 ( 0 % ) ;
; SERDES transmitters ; 0 / 44 ( 0 % ) ;
; SERDES receivers ; 0 / 44 ( 0 % ) ;
; Maximum fan-out node ; CLK8Hz ;
; Maximum fan-out ; 9 ;
; Highest non-global fan-out signal ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] ;
; Highest non-global fan-out ; 5 ;
; Total fan-out ; 74 ;
; Average fan-out ; 2.47 ;
+---------------------------------------------+-------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Input Pins ;
+--------------------------------------------------------------------------------+
Name : CLK12M
Pin # : Y17
I/O Bank : 8
X coordinate : 5
Y coordinate : 0
Cell number : 5
Combinational Fan-Out : 0
Registered Fan-Out : 0
Global : no
Input Register : no
Power Up High : no
PCI I/O Enabled : no
Bus Hold : no
Weak Pull Up : Off
I/O Standard : LVTTL
Termination : Off
Location assigned by : Fitter
Name : CLK8Hz
Pin # : M20
I/O Bank : 1
X coordinate : 0
Y coordinate : 12
Cell number : 0
Combinational Fan-Out : 9
Registered Fan-Out : 0
Global : yes
Input Register : no
Power Up High : no
PCI I/O Enabled : no
Bus Hold : no
Weak Pull Up : Off
I/O Standard : LVTTL
Termination : Off
Location assigned by : Fitter
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Pins ;
+--------------------------------------------------------------------------------+
Name : CODE[0]
Pin # : F1
I/O Bank : 5
X coordinate : 53
Y coordinate : 23
Cell number : 3
Output Register : no
Output Enable Register : no
Power Up High : no
Slow Slew Rate : no
PCI I/O Enabled : no
Open Drain : no
TRI Primitive : no
Bus Hold : no
Weak Pull Up : Off
I/O Standard : LVTTL
Current Strength : 24mA
Termination : Off
Location assigned by : Fitter
Load : 10 pF
Name : CODE[1]
Pin # : F2
I/O Bank : 5
X coordinate : 53
Y coordinate : 23
Cell number : 2
Output Register : no
Output Enable Register : no
Power Up High : no
Slow Slew Rate : no
PCI I/O Enabled : no
Open Drain : no
TRI Primitive : no
Bus Hold : no
Weak Pull Up : Off
I/O Standard : LVTTL
Current Strength : 24mA
Termination : Off
Location assigned by : Fitter
Load : 10 pF
Name : CODE[2]
Pin # : U9
I/O Bank : 7
X coordinate : 36
Y coordinate : 0
Cell number : 5
Output Register : no
Output Enable Register : no
Power Up High : no
Slow Slew Rate : no
PCI I/O Enabled : no
Open Drain : no
TRI Primitive : no
Bus Hold : no
Weak Pull Up : Off
I/O Standard : LVTTL
Current Strength : 24mA
Termination : Off
Location assigned by : Fitter
Load : 10 pF
Name : CODE[3]
Pin # : AA5
I/O Bank : 7
X coordinate : 48
Y coordinate : 0
Cell number : 4
Output Register : no
Output Enable Register : no
Power Up High : no
Slow Slew Rate : no
PCI I/O Enabled : no
Open Drain : no
TRI Primitive : no
Bus Hold : no
Weak Pull Up : Off
I/O Standard : LVTTL
Current Strength : 24mA
Termination : Off
Location assigned by : Fitter
Load : 10 pF
Name : HIGN
Pin # : T8
I/O Bank : 7
X coordinate : 41
Y coordinate : 0
Cell number : 5
Output Register : no
Output Enable Register : no
Power Up High : no
Slow Slew Rate : no
PCI I/O Enabled : no
Open Drain : no
TRI Primitive : no
Bus Hold : no
Weak Pull Up : Off
I/O Standard : LVTTL
Current Strength : 24mA
Termination : Off
Location assigned by : Fitter
Load : 10 pF
Name : SPKS
Pin # : AB5
I/O Bank : 7
X coordinate : 48
Y coordinate : 0
Cell number : 3
Output Register : no
Output Enable Register : no
Power Up High : no
Slow Slew Rate : no
PCI I/O Enabled : no
Open Drain : no
TRI Primitive : no
Bus Hold : no
Weak Pull Up : Off
I/O Standard : LVTTL
Current Strength : 24mA
Termination : Off
Location assigned by : Fitter
Load : 10 pF
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; I/O Bank Usage ;
+--------------------------------------------------------------------------------+
I/O Bank : 1
Usage : 1 / 29 ( 3 % )
VCCIO Voltage : 3.3V
VREF Voltage : --
I/O Bank : 2
Usage : 0 / 30 ( 0 % )
VCCIO Voltage : 3.3V
VREF Voltage : --
I/O Bank : 3
Usage : 0 / 51 ( 0 % )
VCCIO Voltage : 3.3V
VREF Voltage : --
I/O Bank : 4
Usage : 1 / 52 ( 2 % )
VCCIO Voltage : 3.3V
VREF Voltage : --
I/O Bank : 5
Usage : 2 / 29 ( 7 % )
VCCIO Voltage : 3.3V
VREF Voltage : --
I/O Bank : 6
Usage : 0 / 29 ( 0 % )
VCCIO Voltage : 3.3V
VREF Voltage : --
I/O Bank : 7
Usage : 4 / 52 ( 8 % )
VCCIO Voltage : 3.3V
VREF Voltage : --
I/O Bank : 8
Usage : 1 / 51 ( 2 % )
VCCIO Voltage : 3.3V
VREF Voltage : --
I/O Bank : 9
Usage : 0 / 6 ( 0 % )
VCCIO Voltage : 3.3V
VREF Voltage : --
I/O Bank : 10
Usage : 0 / 0 ( -- )
VCCIO Voltage : 3.3V
VREF Voltage : --
I/O Bank : 11
Usage : 0 / 6 ( 0 % )
VCCIO Voltage : 3.3V
VREF Voltage : --
I/O Bank : 12
Usage : 0 / 0 ( -- )
VCCIO Voltage : 3.3V
VREF Voltage : --
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; All Package Pins ;
+--------------------------------------------------------------------------------+
Location : A1
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.5V
I/O Type : --
Termination : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : A2
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
Termination : --
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