we.map.qmsg

出血FPGA,用VHDL做的音乐盒

{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "TONE\[6\] TONETABA.vhd(12) " "Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for \"TONE\[6\]\"" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "TONE\[7\] TONETABA.vhd(12) " "Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for \"TONE\[7\]\"" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "TONE\[8\] TONETABA.vhd(12) " "Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for \"TONE\[8\]\"" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "TONE\[9\] TONETABA.vhd(12) " "Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for \"TONE\[9\]\"" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "TONE\[10\] TONETABA.vhd(12) " "Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for \"TONE\[10\]\"" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom0 lpm_rom0:inst " "Info: Elaborating entity \"lpm_rom0\" for hierarchy \"lpm_rom0:inst\"" {  } { { "we.bdf" "inst" { Schematic "D:/PLD/FPGAlicheng/music/we.bdf" { { 256 192 352 336 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_rom0:inst\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0.tdf" "altsyncram_component" { Text "D:/PLD/FPGAlicheng/music/lpm_rom0.tdf" 45 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_rom0:inst\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"lpm_rom0:inst\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0.tdf" "" { Text "D:/PLD/FPGAlicheng/music/lpm_rom0.tdf" 45 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_f431.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_f431.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_f431 " "Info: Found entity 1: altsyncram_f431" {  } { { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_f431 lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated " "Info: Elaborating entity \"altsyncram_f431\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NoteTabs NoteTabs:inst3 " "Info: Elaborating entity \"NoteTabs\" for hierarchy \"NoteTabs:inst3\"" {  } { { "we.bdf" "inst3" { Schematic "D:/PLD/FPGAlicheng/music/we.bdf" { { 256 24 176 352 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SPEAKER SPEAKER:inst1 " "Info: Elaborating entity \"SPEAKER\" for hierarchy \"SPEAKER:inst1\"" {  } { { "we.bdf" "inst1" { Schematic "D:/PLD/FPGAlicheng/music/we.bdf" { { 280 704 848 376 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "FULLSPKS SPEAKER.vhd(10) " "Warning (10036): Verilog HDL or VHDL warning at SPEAKER.vhd(10): object \"FULLSPKS\" assigned a value but never read" {  } { { "SPEAKER.vhd" "" { Text "D:/PLD/FPGAlicheng/music/SPEAKER.vhd" 10 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SPKS SPEAKER.vhd(7) " "Warning (10034): Output port \"SPKS\" at SPEAKER.vhd(7) has no driver" {  } { { "SPEAKER.vhd" "" { Text "D:/PLD/FPGAlicheng/music/SPEAKER.vhd" 7 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WSGN_EMPTY_SHELL" "SPEAKER " "Warning: Entity \"SPEAKER\" contains only dangling pins" {  } { { "we.bdf" "inst1" { Schematic "D:/PLD/FPGAlicheng/music/we.bdf" { { 280 704 848 376 "inst1" "" } } } }  } 0 0 "Entity \"%1!s!\" contains only dangling pins" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "TONETABA:inst2\|HIGH " "Warning: Latch TONETABA:inst2\|HIGH has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\] " "Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\]" {  } { { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 40 2 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 7 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "TONETABA:inst2\|CODE\[2\] " "Warning: Latch TONETABA:inst2\|CODE\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[2\]" {  } { { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 40 2 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "TONETABA:inst2\|CODE\[1\] " "Warning: Latch TONETABA:inst2\|CODE\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[1\]" {  } { { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 40 2 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "TONETABA:inst2\|CODE\[0\] " "Warning: Latch TONETABA:inst2\|CODE\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[0\]" {  } { { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 40 2 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "SPKS GND " "Warning: Pin \"SPKS\" stuck at GND" {  } { { "we.bdf" "" { Schematic "D:/PLD/FPGAlicheng/music/we.bdf" { { 304 880 1056 320 "SPKS" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "CODE\[3\] GND " "Warning: Pin \"CODE\[3\]\" stuck at GND" {  } { { "we.bdf" "" { Schematic "D:/PLD/FPGAlicheng/music/we.bdf" { { 184 720 896 200 "CODE\[3..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "CLK12M " "Warning: No output dependent on input pin \"CLK12M\"" {  } { { "we.bdf" "" { Schematic "D:/PLD/FPGAlicheng/music/we.bdf" { { 392 328 496 408 "CLK12M" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "31 " "Info: Implemented 31 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "6 " "Info: Implemented 6 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "19 " "Info: Implemented 19 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "4 " "Info: Implemented 4 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 20 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 23 20:21:51 2008 " "Info: Processing ended: Tue Sep 23 20:21:51 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}