we.map.qmsg

出血FPGA,用VHDL做的音乐盒

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 23 20:21:50 2008 " "Info: Processing started: Tue Sep 23 20:21:50 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --lower_priority --read_settings_files=on --write_settings_files=off we -c we " "Info: Command: quartus_map --lower_priority --read_settings_files=on --write_settings_files=off we -c we" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SHUKONGDIV.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SHUKONGDIV.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SHUKONG_DIV-MA " "Info: Found design unit 1: SHUKONG_DIV-MA" {  } { { "SHUKONGDIV.vhd" "" { Text "D:/PLD/FPGAlicheng/music/SHUKONGDIV.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SHUKONG_DIV " "Info: Found entity 1: SHUKONG_DIV" {  } { { "SHUKONGDIV.vhd" "" { Text "D:/PLD/FPGAlicheng/music/SHUKONGDIV.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SPEAKER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SPEAKER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SPEAKER-MA " "Info: Found design unit 1: SPEAKER-MA" {  } { { "SPEAKER.vhd" "" { Text "D:/PLD/FPGAlicheng/music/SPEAKER.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SPEAKER " "Info: Found entity 1: SPEAKER" {  } { { "SPEAKER.vhd" "" { Text "D:/PLD/FPGAlicheng/music/SPEAKER.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "we.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file we.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 we " "Info: Found entity 1: we" {  } { { "we.bdf" "" { Schematic "D:/PLD/FPGAlicheng/music/we.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TONETABA.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TONETABA.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TONETABA-MA " "Info: Found design unit 1: TONETABA-MA" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 TONETABA " "Info: Found entity 1: TONETABA" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NoteTabs.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file NoteTabs.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NoteTabs-one " "Info: Found design unit 1: NoteTabs-one" {  } { { "NoteTabs.vhd" "" { Text "D:/PLD/FPGAlicheng/music/NoteTabs.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 NoteTabs " "Info: Found entity 1: NoteTabs" {  } { { "NoteTabs.vhd" "" { Text "D:/PLD/FPGAlicheng/music/NoteTabs.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/PLD/FPGAlicheng/music/lpm_rom1.tdf " "Warning: Can't analyze file -- file D:/PLD/FPGAlicheng/music/lpm_rom1.tdf is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_rom0.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file lpm_rom0.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom0 " "Info: Found entity 1: lpm_rom0" {  } { { "lpm_rom0.tdf" "" { Text "D:/PLD/FPGAlicheng/music/lpm_rom0.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "we " "Info: Elaborating entity \"we\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TONETABA TONETABA:inst2 " "Info: Elaborating entity \"TONETABA\" for hierarchy \"TONETABA:inst2\"" {  } { { "we.bdf" "inst2" { Schematic "D:/PLD/FPGAlicheng/music/we.bdf" { { 264 424 600 360 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "TONE TONETABA.vhd(12) " "Warning (10631): VHDL Process Statement warning at TONETABA.vhd(12): inferring latch(es) for signal or variable \"TONE\", which holds its previous value in one or more paths through the process" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "CODE TONETABA.vhd(12) " "Warning (10631): VHDL Process Statement warning at TONETABA.vhd(12): inferring latch(es) for signal or variable \"CODE\", which holds its previous value in one or more paths through the process" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "HIGH TONETABA.vhd(12) " "Warning (10631): VHDL Process Statement warning at TONETABA.vhd(12): inferring latch(es) for signal or variable \"HIGH\", which holds its previous value in one or more paths through the process" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "HIGH TONETABA.vhd(12) " "Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for \"HIGH\"" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "CODE\[0\] TONETABA.vhd(12) " "Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for \"CODE\[0\]\"" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "CODE\[1\] TONETABA.vhd(12) " "Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for \"CODE\[1\]\"" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "CODE\[2\] TONETABA.vhd(12) " "Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for \"CODE\[2\]\"" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "CODE\[3\] TONETABA.vhd(12) " "Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for \"CODE\[3\]\"" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "TONE\[0\] TONETABA.vhd(12) " "Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for \"TONE\[0\]\"" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "TONE\[1\] TONETABA.vhd(12) " "Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for \"TONE\[1\]\"" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "TONE\[2\] TONETABA.vhd(12) " "Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for \"TONE\[2\]\"" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "TONE\[3\] TONETABA.vhd(12) " "Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for \"TONE\[3\]\"" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "TONE\[4\] TONETABA.vhd(12) " "Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for \"TONE\[4\]\"" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "TONE\[5\] TONETABA.vhd(12) " "Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for \"TONE\[5\]\"" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}