we.tan.qmsg

出血FPGA,用VHDL做的音乐盒

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "TONETABA:inst2\|Mux4~31 " "Info: Detected gated clock \"TONETABA:inst2\|Mux4~31\" as buffer" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 14 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "TONETABA:inst2\|Mux4~31" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[0\] " "Info: Detected ripple clock \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[0\]\" as buffer" {  } { { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 40 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[1\] " "Info: Detected ripple clock \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[1\]\" as buffer" {  } { { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 40 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[2\] " "Info: Detected ripple clock \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[2\]\" as buffer" {  } { { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 40 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\] " "Info: Detected ripple clock \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\]\" as buffer" {  } { { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 40 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK8Hz memory lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|ram_block1a3~porta_address_reg0 memory lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\] 290.87 MHz 3.438 ns Internal " "Info: Clock \"CLK8Hz\" has Internal fmax of 290.87 MHz between source memory \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|ram_block1a3~porta_address_reg0\" and destination memory \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\]\" (period= 3.438 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.875 ns + Longest memory memory " "Info: + Longest memory to memory delay is 2.875 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|ram_block1a3~porta_address_reg0 1 MEM M4K_X37_Y23 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X37_Y23; Fanout = 4; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|ram_block1a3~porta_address_reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 103 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.875 ns) 2.875 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\] 2 MEM M4K_X37_Y23 5 " "Info: 2: + IC(0.000 ns) + CELL(2.875 ns) = 2.875 ns; Loc. = M4K_X37_Y23; Fanout = 5; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.875 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } "NODE_NAME" } } { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.875 ns ( 100.00 % ) " "Info: Total cell delay = 2.875 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.875 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.875 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } { 0.000ns 0.000ns } { 0.000ns 2.875ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.012 ns - Smallest " "Info: - Smallest clock skew is -0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK8Hz destination 2.861 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK8Hz\" to destination memory is 2.861 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK8Hz 1 CLK PIN_M20 20 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 20; CLK Node = 'CLK8Hz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK8Hz } "NODE_NAME" } } { "we.bdf" "" { Schematic "D:/PLD/FPGAlicheng/music/we.bdf" { { 288 -208 -40 304 "CLK8Hz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.533 ns) + CELL(0.500 ns) 2.861 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\] 2 MEM M4K_X37_Y23 5 " "Info: 2: + IC(1.533 ns) + CELL(0.500 ns) = 2.861 ns; Loc. = M4K_X37_Y23; Fanout = 5; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.033 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } "NODE_NAME" } } { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.328 ns ( 46.42 % ) " "Info: Total cell delay = 1.328 ns ( 46.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.533 ns ( 53.58 % ) " "Info: Total interconnect delay = 1.533 ns ( 53.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.861 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.861 ns" { CLK8Hz CLK8Hz~out0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.828ns 0.500ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK8Hz source 2.873 ns - Longest memory " "Info: - Longest clock path from clock \"CLK8Hz\" to source memory is 2.873 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK8Hz 1 CLK PIN_M20 20 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 20; CLK Node = 'CLK8Hz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK8Hz } "NODE_NAME" } } { "we.bdf" "" { Schematic "D:/PLD/FPGAlicheng/music/we.bdf" { { 288 -208 -40 304 "CLK8Hz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.533 ns) + CELL(0.512 ns) 2.873 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|ram_block1a3~porta_address_reg0 2 MEM M4K_X37_Y23 4 " "Info: 2: + IC(1.533 ns) + CELL(0.512 ns) = 2.873 ns; Loc. = M4K_X37_Y23; Fanout = 4; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|ram_block1a3~porta_address_reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.045 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 103 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.340 ns ( 46.64 % ) " "Info: Total cell delay = 1.340 ns ( 46.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.533 ns ( 53.36 % ) " "Info: Total interconnect delay = 1.533 ns ( 53.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.873 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.873 ns" { CLK8Hz CLK8Hz~out0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0 } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.828ns 0.512ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.861 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.861 ns" { CLK8Hz CLK8Hz~out0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.828ns 0.500ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.873 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.873 ns" { CLK8Hz CLK8Hz~out0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0 } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.828ns 0.512ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.420 ns + " "Info: + Micro clock to output delay of source is 0.420 ns" {  } { { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 103 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.131 ns + " "Info: + Micro setup delay of destination is 0.131 ns" {  } { { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.875 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.875 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } { 0.000ns 0.000ns } { 0.000ns 2.875ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.861 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.861 ns" { CLK8Hz CLK8Hz~out0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.828ns 0.500ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.873 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.873 ns" { CLK8Hz CLK8Hz~out0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0 } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.828ns 0.512ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK8Hz 10 " "Warning: Circuit may not operate. Detected 10 non-operational path(s) clocked by clock \"CLK8Hz\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\] TONETABA:inst2\|HIGH CLK8Hz 4.193 ns " "Info: Found hold time violation between source  pin or register \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\]\" and destination pin or register \"TONETABA:inst2\|HIGH\" for clock \"CLK8Hz\" (Hold time is 4.193 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.878 ns + Largest " "Info: + Largest clock skew is 5.878 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK8Hz destination 8.739 ns + Longest register " "Info: + Longest clock path from clock \"CLK8Hz\" to destination register is 8.739 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK8Hz 1 CLK PIN_M20 20 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 20; CLK Node = 'CLK8Hz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK8Hz } "NODE_NAME" } } { "we.bdf" "" { Schematic "D:/PLD/FPGAlicheng/music/we.bdf" { { 288 -208 -40 304 "CLK8Hz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.533 ns) + CELL(0.991 ns) 3.352 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[2\] 2 MEM M4K_X37_Y23 2 " "Info: 2: + IC(1.533 ns) + CELL(0.991 ns) = 3.352 ns; Loc. = M4K_X37_Y23; Fanout = 2; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.524 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2] } "NODE_NAME" } } { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.366 ns) 4.500 ns TONETABA:inst2\|Mux4~31 3 COMB LC_X39_Y23_N4 4 " "Info: 3: + IC(0.782 ns) + CELL(0.366 ns) = 4.500 ns; Loc. = LC_X39_Y23_N4; Fanout = 4; COMB Node = 'TONETABA:inst2\|Mux4~31'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.148 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2] TONETABA:inst2|Mux4~31 } "NODE_NAME" } } { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.164 ns) + CELL(0.075 ns) 8.739 ns TONETABA:inst2\|HIGH 4 REG LC_X39_Y23_N1 1 " "Info: 4: + IC(4.164 ns) + CELL(0.075 ns) = 8.739 ns; Loc. = LC_X39_Y23_N1; Fanout = 1; REG Node = 'TONETABA:inst2\|HIGH'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.239 ns" { TONETABA:inst2|Mux4~31 TONETABA:inst2|HIGH } "NODE_NAME" } } { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.260 ns ( 25.86 % ) " "Info: Total cell delay = 2.260 ns ( 25.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.479 ns ( 74.14 % ) " "Info: Total interconnect delay = 6.479 ns ( 74.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.739 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2] TONETABA:inst2|Mux4~31 TONETABA:inst2|HIGH } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.739 ns" { CLK8Hz CLK8Hz~out0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2] TONETABA:inst2|Mux4~31 TONETABA:inst2|HIGH } { 0.000ns 0.000ns 1.533ns 0.782ns 4.164ns } { 0.000ns 0.828ns 0.991ns 0.366ns 0.075ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK8Hz source 2.861 ns - Shortest memory " "Info: - Shortest clock path from clock \"CLK8Hz\" to source memory is 2.861 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK8Hz 1 CLK PIN_M20 20 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 20; CLK Node = 'CLK8Hz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK8Hz } "NODE_NAME" } } { "we.bdf" "" { Schematic "D:/PLD/FPGAlicheng/music/we.bdf" { { 288 -208 -40 304 "CLK8Hz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.533 ns) + CELL(0.500 ns) 2.861 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\] 2 MEM M4K_X37_Y23 5 " "Info: 2: + IC(1.533 ns) + CELL(0.500 ns) = 2.861 ns; Loc. = M4K_X37_Y23; Fanout = 5; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.033 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } "NODE_NAME" } } { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.328 ns ( 46.42 % ) " "Info: Total cell delay = 1.328 ns ( 46.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.533 ns ( 53.58 % ) " "Info: Total interconnect delay = 1.533 ns ( 53.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.861 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.861 ns" { CLK8Hz CLK8Hz~out0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.828ns 0.500ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.739 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2] TONETABA:inst2|Mux4~31 TONETABA:inst2|HIGH } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.739 ns" { CLK8Hz CLK8Hz~out0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2] TONETABA:inst2|Mux4~31 TONETABA:inst2|HIGH } { 0.000ns 0.000ns 1.533ns 0.782ns 4.164ns } { 0.000ns 0.828ns 0.991ns 0.366ns 0.075ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.861 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.861 ns" { CLK8Hz CLK8Hz~out0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.828ns 0.500ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.420 ns - " "Info: - Micro clock to output delay of source is 0.420 ns" {  } { { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.265 ns - Shortest memory register " "Info: - Shortest memory to register delay is 1.265 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.071 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\] 1 MEM M4K_X37_Y23 5 " "Info: 1: + IC(0.000 ns) + CELL(0.071 ns) = 0.071 ns; Loc. = M4K_X37_Y23; Fanout = 5; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } "NODE_NAME" } } { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.828 ns) + CELL(0.366 ns) 1.265 ns TONETABA:inst2\|HIGH 2 REG LC_X39_Y23_N1 1 " "Info: 2: + IC(0.828 ns) + CELL(0.366 ns) = 1.265 ns; Loc. = LC_X39_Y23_N1; Fanout = 1; REG Node = 'TONETABA:inst2\|HIGH'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.194 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] TONETABA:inst2|HIGH } "NODE_NAME" } } { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.437 ns ( 34.55 % ) " "Info: Total cell delay = 0.437 ns ( 34.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.828 ns ( 65.45 % ) " "Info: Total interconnect delay = 0.828 ns ( 65.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.265 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] TONETABA:inst2|HIGH } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.265 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] TONETABA:inst2|HIGH } { 0.000ns 0.828ns } { 0.071ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 7 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.739 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2] TONETABA:inst2|Mux4~31 TONETABA:inst2|HIGH } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.739 ns" { CLK8Hz CLK8Hz~out0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2] TONETABA:inst2|Mux4~31 TONETABA:inst2|HIGH } { 0.000ns 0.000ns 1.533ns 0.782ns 4.164ns } { 0.000ns 0.828ns 0.991ns 0.366ns 0.075ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.861 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.861 ns" { CLK8Hz CLK8Hz~out0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.828ns 0.500ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.265 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] TONETABA:inst2|HIGH } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.265 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3] TONETABA:inst2|HIGH } { 0.000ns 0.828ns } { 0.071ns 0.366ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK8Hz CODE\[2\] TONETABA:inst2\|CODE\[2\] 13.040 ns register " "Info: tco from clock \"CLK8Hz\" to destination pin \"CODE\[2\]\" through register \"TONETABA:inst2\|CODE\[2\]\" is 13.040 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK8Hz source 8.738 ns + Longest register " "Info: + Longest clock path from clock \"CLK8Hz\" to source register is 8.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK8Hz 1 CLK PIN_M20 20 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 20; CLK Node = 'CLK8Hz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK8Hz } "NODE_NAME" } } { "we.bdf" "" { Schematic "D:/PLD/FPGAlicheng/music/we.bdf" { { 288 -208 -40 304 "CLK8Hz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.533 ns) + CELL(0.991 ns) 3.352 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[2\] 2 MEM M4K_X37_Y23 2 " "Info: 2: + IC(1.533 ns) + CELL(0.991 ns) = 3.352 ns; Loc. = M4K_X37_Y23; Fanout = 2; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_f431:auto_generated\|q_a\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.524 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2] } "NODE_NAME" } } { "db/altsyncram_f431.tdf" "" { Text "D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.366 ns) 4.500 ns TONETABA:inst2\|Mux4~31 3 COMB LC_X39_Y23_N4 4 " "Info: 3: + IC(0.782 ns) + CELL(0.366 ns) = 4.500 ns; Loc. = LC_X39_Y23_N4; Fanout = 4; COMB Node = 'TONETABA:inst2\|Mux4~31'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.148 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2] TONETABA:inst2|Mux4~31 } "NODE_NAME" } } { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.163 ns) + CELL(0.075 ns) 8.738 ns TONETABA:inst2\|CODE\[2\] 4 REG LC_X39_Y23_N3 1 " "Info: 4: + IC(4.163 ns) + CELL(0.075 ns) = 8.738 ns; Loc. = LC_X39_Y23_N3; Fanout = 1; REG Node = 'TONETABA:inst2\|CODE\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.238 ns" { TONETABA:inst2|Mux4~31 TONETABA:inst2|CODE[2] } "NODE_NAME" } } { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.260 ns ( 25.86 % ) " "Info: Total cell delay = 2.260 ns ( 25.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.478 ns ( 74.14 % ) " "Info: Total interconnect delay = 6.478 ns ( 74.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.738 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2] TONETABA:inst2|Mux4~31 TONETABA:inst2|CODE[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.738 ns" { CLK8Hz CLK8Hz~out0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2] TONETABA:inst2|Mux4~31 TONETABA:inst2|CODE[2] } { 0.000ns 0.000ns 1.533ns 0.782ns 4.163ns } { 0.000ns 0.828ns 0.991ns 0.366ns 0.075ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.302 ns + Longest register pin " "Info: + Longest register to pin delay is 4.302 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TONETABA:inst2\|CODE\[2\] 1 REG LC_X39_Y23_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X39_Y23_N3; Fanout = 1; REG Node = 'TONETABA:inst2\|CODE\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TONETABA:inst2|CODE[2] } "NODE_NAME" } } { "TONETABA.vhd" "" { Text "D:/PLD/FPGAlicheng/music/TONETABA.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.898 ns) + CELL(2.404 ns) 4.302 ns CODE\[2\] 2 PIN PIN_U9 0 " "Info: 2: + IC(1.898 ns) + CELL(2.404 ns) = 4.302 ns; Loc. = PIN_U9; Fanout = 0; PIN Node = 'CODE\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.302 ns" { TONETABA:inst2|CODE[2] CODE[2] } "NODE_NAME" } } { "we.bdf" "" { Schematic "D:/PLD/FPGAlicheng/music/we.bdf" { { 184 720 896 200 "CODE\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 55.88 % ) " "Info: Total cell delay = 2.404 ns ( 55.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.898 ns ( 44.12 % ) " "Info: Total interconnect delay = 1.898 ns ( 44.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.302 ns" { TONETABA:inst2|CODE[2] CODE[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.302 ns" { TONETABA:inst2|CODE[2] CODE[2] } { 0.000ns 1.898ns } { 0.000ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.738 ns" { CLK8Hz lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2] TONETABA:inst2|Mux4~31 TONETABA:inst2|CODE[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.738 ns" { CLK8Hz CLK8Hz~out0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2] TONETABA:inst2|Mux4~31 TONETABA:inst2|CODE[2] } { 0.000ns 0.000ns 1.533ns 0.782ns 4.163ns } { 0.000ns 0.828ns 0.991ns 0.366ns 0.075ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.302 ns" { TONETABA:inst2|CODE[2] CODE[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.302 ns" { TONETABA:inst2|CODE[2] CODE[2] } { 0.000ns 1.898ns } { 0.000ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}