we.hier_info

出血FPGA,用VHDL做的音乐盒

|we
HIGN <= TONETABA:inst2.HIGH
CLK8Hz => lpm_rom0:inst.clock
CLK8Hz => NoteTabs:inst3.clk
SPKS <= SPEAKER:inst1.SPKS
CLK12M => SPEAKER:inst1.CLK
CODE[0] <= TONETABA:inst2.CODE[0]
CODE[1] <= TONETABA:inst2.CODE[1]
CODE[2] <= TONETABA:inst2.CODE[2]
CODE[3] <= TONETABA:inst2.CODE[3]


|we|TONETABA:inst2
INDEX[0] => Mux0.IN19
INDEX[0] => Mux1.IN19
INDEX[0] => Mux2.IN19
INDEX[0] => Mux3.IN19
INDEX[0] => Mux4.IN19
INDEX[0] => Mux5.IN19
INDEX[0] => Mux6.IN19
INDEX[0] => Mux7.IN19
INDEX[0] => Mux8.IN19
INDEX[0] => Mux9.IN19
INDEX[0] => Mux10.IN19
INDEX[0] => Mux11.IN19
INDEX[0] => Mux12.IN19
INDEX[0] => Mux13.IN19
INDEX[0] => Mux14.IN19
INDEX[0] => Mux15.IN19
INDEX[0] => Mux16.IN19
INDEX[0] => Mux17.IN19
INDEX[1] => Mux0.IN18
INDEX[1] => Mux1.IN18
INDEX[1] => Mux2.IN18
INDEX[1] => Mux3.IN18
INDEX[1] => Mux4.IN18
INDEX[1] => Mux5.IN18
INDEX[1] => Mux6.IN18
INDEX[1] => Mux7.IN18
INDEX[1] => Mux8.IN18
INDEX[1] => Mux9.IN18
INDEX[1] => Mux10.IN18
INDEX[1] => Mux11.IN18
INDEX[1] => Mux12.IN18
INDEX[1] => Mux13.IN18
INDEX[1] => Mux14.IN18
INDEX[1] => Mux15.IN18
INDEX[1] => Mux16.IN18
INDEX[1] => Mux17.IN18
INDEX[2] => Mux0.IN17
INDEX[2] => Mux1.IN17
INDEX[2] => Mux2.IN17
INDEX[2] => Mux3.IN17
INDEX[2] => Mux4.IN17
INDEX[2] => Mux5.IN17
INDEX[2] => Mux6.IN17
INDEX[2] => Mux7.IN17
INDEX[2] => Mux8.IN17
INDEX[2] => Mux9.IN17
INDEX[2] => Mux10.IN17
INDEX[2] => Mux11.IN17
INDEX[2] => Mux12.IN17
INDEX[2] => Mux13.IN17
INDEX[2] => Mux14.IN17
INDEX[2] => Mux15.IN17
INDEX[2] => Mux16.IN17
INDEX[2] => Mux17.IN17
INDEX[3] => Mux0.IN16
INDEX[3] => Mux1.IN16
INDEX[3] => Mux2.IN16
INDEX[3] => Mux3.IN16
INDEX[3] => Mux4.IN16
INDEX[3] => Mux5.IN16
INDEX[3] => Mux6.IN16
INDEX[3] => Mux7.IN16
INDEX[3] => Mux8.IN16
INDEX[3] => Mux9.IN16
INDEX[3] => Mux10.IN16
INDEX[3] => Mux11.IN16
INDEX[3] => Mux12.IN16
INDEX[3] => Mux13.IN16
INDEX[3] => Mux14.IN16
INDEX[3] => Mux15.IN16
INDEX[3] => Mux16.IN16
INDEX[3] => Mux17.IN16
CODE[0] <= CODE[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
CODE[1] <= CODE[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
CODE[2] <= CODE[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
CODE[3] <= CODE[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
HIGH <= HIGH$latch.DB_MAX_OUTPUT_PORT_TYPE
TONE[0] <= TONE[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
TONE[1] <= TONE[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
TONE[2] <= TONE[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
TONE[3] <= TONE[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
TONE[4] <= TONE[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
TONE[5] <= TONE[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
TONE[6] <= TONE[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
TONE[7] <= TONE[7]$latch.DB_MAX_OUTPUT_PORT_TYPE
TONE[8] <= TONE[8]$latch.DB_MAX_OUTPUT_PORT_TYPE
TONE[9] <= TONE[9]$latch.DB_MAX_OUTPUT_PORT_TYPE
TONE[10] <= TONE[10]$latch.DB_MAX_OUTPUT_PORT_TYPE


|we|lpm_rom0:inst
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]


|we|lpm_rom0:inst|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_f431:auto_generated.address_a[0]
address_a[1] => altsyncram_f431:auto_generated.address_a[1]
address_a[2] => altsyncram_f431:auto_generated.address_a[2]
address_a[3] => altsyncram_f431:auto_generated.address_a[3]
address_a[4] => altsyncram_f431:auto_generated.address_a[4]
address_a[5] => altsyncram_f431:auto_generated.address_a[5]
address_a[6] => altsyncram_f431:auto_generated.address_a[6]
address_a[7] => altsyncram_f431:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_f431:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_f431:auto_generated.q_a[0]
q_a[1] <= altsyncram_f431:auto_generated.q_a[1]
q_a[2] <= altsyncram_f431:auto_generated.q_a[2]
q_a[3] <= altsyncram_f431:auto_generated.q_a[3]
q_b[0] <= <GND>


|we|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT


|we|NoteTabs:inst3
clk => Counter[0].CLK
clk => Counter[1].CLK
clk => Counter[2].CLK
clk => Counter[3].CLK
clk => Counter[4].CLK
clk => Counter[5].CLK
clk => Counter[6].CLK
clk => Counter[7].CLK
CounterOUT[0] <= Counter[0].DB_MAX_OUTPUT_PORT_TYPE
CounterOUT[1] <= Counter[1].DB_MAX_OUTPUT_PORT_TYPE
CounterOUT[2] <= Counter[2].DB_MAX_OUTPUT_PORT_TYPE
CounterOUT[3] <= Counter[3].DB_MAX_OUTPUT_PORT_TYPE
CounterOUT[4] <= Counter[4].DB_MAX_OUTPUT_PORT_TYPE
CounterOUT[5] <= Counter[5].DB_MAX_OUTPUT_PORT_TYPE
CounterOUT[6] <= Counter[6].DB_MAX_OUTPUT_PORT_TYPE
CounterOUT[7] <= Counter[7].DB_MAX_OUTPUT_PORT_TYPE


|we|SPEAKER:inst1
CLK => ~NO_FANOUT~
TONE[0] => ~NO_FANOUT~
TONE[1] => ~NO_FANOUT~
TONE[2] => ~NO_FANOUT~
TONE[3] => ~NO_FANOUT~
TONE[4] => ~NO_FANOUT~
TONE[5] => ~NO_FANOUT~
TONE[6] => ~NO_FANOUT~
TONE[7] => ~NO_FANOUT~
TONE[8] => ~NO_FANOUT~
TONE[9] => ~NO_FANOUT~
TONE[10] => ~NO_FANOUT~
SPKS <= <GND>