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<TITLE>Flow report for we</TITLE>
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<H1>Flow report for we</H1>
<H3>Tue Sep 23 20:22:06 2008<BR>
Version 6.0 Build 178 04/27/2006 SJ Full Version</H3>
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<P><HR></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Table of Contents</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<OL>
<LI><A HREF="#1">Legal Notice</A></LI>
<LI><A HREF="#2">Flow Summary</A></LI>
<LI><A HREF="#3">Flow Settings</A></LI>
<LI><A HREF="#4">Flow Non-Default Global Settings</A></LI>
<LI><A HREF="#5">Flow Elapsed Time</A></LI>
<LI><A HREF="#6">Flow Log</A></LI>
</OL>
<P><A NAME="1"><HR></A></P>
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<TD><H2>Legal Notice</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<PRE>Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
</PRE>
<P><A NAME="2"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Flow Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle">
<TD ALIGN="LEFT">Flow Status</TH>
<TD ALIGN="LEFT">Successful - Tue Sep 23 20:22:06 2008</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Quartus II Version</TD>
<TD ALIGN="LEFT">6.0 Build 178 04/27/2006 SJ Full Version</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Revision Name</TD>
<TD ALIGN="LEFT">we</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Top-level Entity Name</TD>
<TD ALIGN="LEFT">we</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Family</TD>
<TD ALIGN="LEFT">Stratix</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Met timing requirements</TD>
<TD ALIGN="LEFT">No</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total logic elements</TD>
<TD ALIGN="LEFT">20 / 10,570 ( < 1 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total pins</TD>
<TD ALIGN="LEFT">8 / 336 ( 2 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total virtual pins</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total memory bits</TD>
<TD ALIGN="LEFT">1,024 / 920,448 ( < 1 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">DSP block 9-bit elements</TD>
<TD ALIGN="LEFT">0 / 48 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total PLLs</TD>
<TD ALIGN="LEFT">0 / 6 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total DLLs</TD>
<TD ALIGN="LEFT">0 / 2 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Device</TD>
<TD ALIGN="LEFT">EP1S10F484C5</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Timing Models</TD>
<TD ALIGN="LEFT">Final</TD>
</TR>
</TABLE>
<P><A NAME="3"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Flow Settings</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Option</TH>
<TH>Setting</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Start date & time</TD>
<TD ALIGN="LEFT">09/23/2008 20:21:50</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Main task</TD>
<TD ALIGN="LEFT">Compilation</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Revision Name</TD>
<TD ALIGN="LEFT">we</TD>
</TR>
</TABLE>
<P><A NAME="4"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Flow Non-Default Global Settings</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Assignment Name</TH>
<TH>Value</TH>
<TH>Default Value</TH>
<TH>Entity Name</TH>
<TH>Section Id</TH>
</TR>
</TABLE>
<P><A NAME="5"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Flow Elapsed Time</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Module Name</TH>
<TH>Elapsed Time</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Analysis & Synthesis</TD>
<TD ALIGN="LEFT">00:00:02</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Fitter</TD>
<TD ALIGN="LEFT">00:00:06</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Assembler</TD>
<TD ALIGN="LEFT">00:00:03</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Timing Analyzer</TD>
<TD ALIGN="LEFT">00:00:01</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total</TD>
<TD ALIGN="LEFT">00:00:12</TD>
</TR>
</TABLE>
<P><A NAME="6"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Flow Log</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<PRE>quartus_map --lower_priority --read_settings_files=on --write_settings_files=off we -c we
quartus_fit --lower_priority --read_settings_files=off --write_settings_files=off we -c we
quartus_asm --lower_priority --read_settings_files=off --write_settings_files=off we -c we
quartus_tan --lower_priority --read_settings_files=off --write_settings_files=off we -c we --timing_analysis_only
</PRE>
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