we.tan.rpt

出血FPGA,用VHDL做的音乐盒

Timing Analyzer report for we
Tue Sep 23 20:22:06 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'CLK8Hz'
  6. Clock Hold: 'CLK8Hz'
  7. tco
  8. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                        ;
+--------------------------------------------------------------------------------+
Type          : Worst-case tco
Slack         : N/A
Required Time : None
Actual Time   : 13.040 ns
From          : TONETABA:inst2|CODE[2]
To            : CODE[2]
From Clock    : CLK8Hz
To Clock      : --
Failed Paths  : 0

Type          : Clock Setup: 'CLK8Hz'
Slack         : N/A
Required Time : None
Actual Time   : 290.87 MHz ( period = 3.438 ns )
From          : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg7
To            : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[0]
From Clock    : CLK8Hz
To Clock      : CLK8Hz
Failed Paths  : 0

Type          : Clock Hold: 'CLK8Hz'
Slack         : Not operational: Clock Skew > Data Delay
Required Time : None
Actual Time   : N/A
From          : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]
To            : TONETABA:inst2|HIGH
From Clock    : CLK8Hz
To Clock      : CLK8Hz
Failed Paths  : 10

Type          : Total number of failed paths
Slack         : 
Required Time : 
Actual Time   : 
From          : 
To            : 
From Clock    : 
To Clock      : 
Failed Paths  : 10
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                       ;
+--------------------------------------------------------------------------------+
Option      : Device Name
Setting     : EP1S10F484C5
From        : 
To          : 
Entity Name : 

Option      : Timing Models
Setting     : Final
From        : 
To          : 
Entity Name : 

Option      : Number of source nodes to report per destination node
Setting     : 10
From        : 
To          : 
Entity Name : 

Option      : Number of destination nodes to report
Setting     : 10
From        : 
To          : 
Entity Name : 

Option      : Number of paths to report
Setting     : 200
From        : 
To          : 
Entity Name : 

Option      : Report Minimum Timing Checks
Setting     : Off
From        : 
To          : 
Entity Name : 

Option      : Use Fast Timing Models
Setting     : Off
From        : 
To          : 
Entity Name : 

Option      : Report IO Paths Separately
Setting     : Off
From        : 
To          : 
Entity Name : 

Option      : Default hold multicycle
Setting     : Same As Multicycle
From        : 
To          : 
Entity Name : 

Option      : Cut paths between unrelated clock domains
Setting     : On
From        : 
To          : 
Entity Name : 

Option      : Cut off read during write signal paths
Setting     : On
From        : 
To          : 
Entity Name : 

Option      : Cut off feedback from I/O pins
Setting     : On
From        : 
To          : 
Entity Name : 

Option      : Report Combined Fast/Slow Timing
Setting     : Off
From        : 
To          : 
Entity Name : 

Option      : Ignore Clock Settings
Setting     : Off
From        : 
To          : 
Entity Name : 

Option      : Analyze latches as synchronous elements
Setting     : On
From        : 
To          : 
Entity Name : 

Option      : Enable Recovery/Removal analysis
Setting     : Off
From        : 
To          : 
Entity Name : 

Option      : Enable Clock Latency
Setting     : Off
From        : 
To          : 
Entity Name : 

Option      : Use TimeQuest Timing Analyzer
Setting     : Off
From        : 
To          : 
Entity Name : 
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Clock Settings Summary                                                         ;
+--------------------------------------------------------------------------------+
Clock Node Name       : CLK8Hz
Clock Setting Name    : 
Type                  : User Pin
Fmax Requirement      : None
Early Latency         : 0.000 ns
Late Latency          : 0.000 ns
Based on              : --
Multiply Base Fmax by : N/A
Divide Base Fmax by   : N/A
Offset                : N/A
Phase offset          : 
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Clock Setup: 'CLK8Hz'                                                          ;
+--------------------------------------------------------------------------------+
Slack                       : N/A
Actual fmax (period)        : 290.87 MHz ( period = 3.438 ns )
From                        : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0
To                          : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]
From Clock                  : CLK8Hz
To Clock                    : CLK8Hz
Required Setup Relationship : None
Required Longest P2P Time   : None
Actual Longest P2P Time     : 2.875 ns

Slack                       : N/A
Actual fmax (period)        : 290.87 MHz ( period = 3.438 ns )
From                        : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg1
To                          : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]
From Clock                  : CLK8Hz
To Clock                    : CLK8Hz
Required Setup Relationship : None
Required Longest P2P Time   : None
Actual Longest P2P Time     : 2.875 ns

Slack                       : N/A
Actual fmax (period)        : 290.87 MHz ( period = 3.438 ns )
From                        : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg2
To                          : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]
From Clock                  : CLK8Hz
To Clock                    : CLK8Hz
Required Setup Relationship : None
Required Longest P2P Time   : None
Actual Longest P2P Time     : 2.875 ns

Slack                       : N/A
Actual fmax (period)        : 290.87 MHz ( period = 3.438 ns )
From                        : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg3
To                          : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]
From Clock                  : CLK8Hz
To Clock                    : CLK8Hz
Required Setup Relationship : None
Required Longest P2P Time   : None
Actual Longest P2P Time     : 2.875 ns

Slack                       : N/A
Actual fmax (period)        : 290.87 MHz ( period = 3.438 ns )
From                        : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg4
To                          : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]
From Clock                  : CLK8Hz
To Clock                    : CLK8Hz
Required Setup Relationship : None
Required Longest P2P Time   : None
Actual Longest P2P Time     : 2.875 ns

Slack                       : N/A
Actual fmax (period)        : 290.87 MHz ( period = 3.438 ns )
From                        : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg5
To                          : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]
From Clock                  : CLK8Hz
To Clock                    : CLK8Hz
Required Setup Relationship : None
Required Longest P2P Time   : None
Actual Longest P2P Time     : 2.875 ns

Slack                       : N/A
Actual fmax (period)        : 290.87 MHz ( period = 3.438 ns )
From                        : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg6
To                          : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]
From Clock                  : CLK8Hz
To Clock                    : CLK8Hz
Required Setup Relationship : None
Required Longest P2P Time   : None
Actual Longest P2P Time     : 2.875 ns

Slack                       : N/A
Actual fmax (period)        : 290.87 MHz ( period = 3.438 ns )
From                        : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg7
To                          : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]
From Clock                  : CLK8Hz
To Clock                    : CLK8Hz
Required Setup Relationship : None
Required Longest P2P Time   : None
Actual Longest P2P Time     : 2.875 ns