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<H1>Fitter report for we</H1>
<H3>Tue Sep 23 20:21:59 2008<BR>
Version 6.0 Build 178 04/27/2006 SJ Full Version</H3>
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<P><HR></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Table of Contents</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<OL>
<LI><A HREF="#1">Legal Notice</A></LI>
<LI><A HREF="#2">Fitter Summary</A></LI>
<LI><A HREF="#3">Fitter Settings</A></LI>
<LI><A HREF="#4">Fitter Equations</A></LI>
<LI><A HREF="#5">Pin-Out File</A></LI>
<LI><A HREF="#6">Fitter Resource Usage Summary</A></LI>
<LI><A HREF="#7">Input Pins</A></LI>
<LI><A HREF="#8">Output Pins</A></LI>
<LI><A HREF="#9">I/O Bank Usage</A></LI>
<LI><A HREF="#10">All Package Pins</A></LI>
<LI><A HREF="#11">Output Pin Default Load For Reported TCO</A></LI>
<LI><A HREF="#12">Fitter Resource Utilization by Entity</A></LI>
<LI><A HREF="#13">Delay Chain Summary</A></LI>
<LI><A HREF="#14">Pad To Core Delay Chain Fanout</A></LI>
<LI><A HREF="#15">Control Signals</A></LI>
<LI><A HREF="#16">Global & Other Fast Signals</A></LI>
<LI><A HREF="#17">Non-Global High Fan-Out Signals</A></LI>
<LI><A HREF="#18">Fitter RAM Summary</A></LI>
<LI><A HREF="#19">Interconnect Usage Summary</A></LI>
<LI><A HREF="#20">LAB Logic Elements</A></LI>
<LI><A HREF="#21">LAB-wide Signals</A></LI>
<LI><A HREF="#22">LAB Signals Sourced</A></LI>
<LI><A HREF="#23">LAB Signals Sourced Out</A></LI>
<LI><A HREF="#24">LAB Distinct Inputs</A></LI>
<LI><A HREF="#25">Fitter Device Options</A></LI>
<LI><A HREF="#26">Advanced Data - General</A></LI>
<LI><A HREF="#27">Advanced Data - Placement Preparation</A></LI>
<LI><A HREF="#28">Advanced Data - Placement</A></LI>
<LI><A HREF="#29">Advanced Data - Routing</A></LI>
<LI><A HREF="#30">Fitter Messages</A></LI>
<LI><A HREF="#31">Fitter Suppressed Messages</A></LI>
</OL>
<P><A NAME="1"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Legal Notice</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<PRE>Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
</PRE>
<P><A NAME="2"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Fitter Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle">
<TD ALIGN="LEFT">Fitter Status</TH>
<TD ALIGN="LEFT">Successful - Tue Sep 23 20:21:59 2008</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Quartus II Version</TD>
<TD ALIGN="LEFT">6.0 Build 178 04/27/2006 SJ Full Version</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Revision Name</TD>
<TD ALIGN="LEFT">we</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Top-level Entity Name</TD>
<TD ALIGN="LEFT">we</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Family</TD>
<TD ALIGN="LEFT">Stratix</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Device</TD>
<TD ALIGN="LEFT">EP1S10F484C5</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Timing Models</TD>
<TD ALIGN="LEFT">Final</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total logic elements</TD>
<TD ALIGN="LEFT">20 / 10,570 ( < 1 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total pins</TD>
<TD ALIGN="LEFT">8 / 336 ( 2 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total virtual pins</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total memory bits</TD>
<TD ALIGN="LEFT">1,024 / 920,448 ( < 1 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">DSP block 9-bit elements</TD>
<TD ALIGN="LEFT">0 / 48 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total PLLs</TD>
<TD ALIGN="LEFT">0 / 6 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total DLLs</TD>
<TD ALIGN="LEFT">0 / 2 ( 0 % )</TD>
</TR>
</TABLE>
<P><A NAME="3"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Fitter Settings</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Option</TH>
<TH>Setting</TH>
<TH>Default Value</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Device</TD>
<TD ALIGN="LEFT">AUTO</TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Use smart compilation</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Router Timing Optimization Level</TD>
<TD ALIGN="LEFT">Normal</TD>
<TD ALIGN="LEFT">Normal</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Placement Effort Multiplier</TD>
<TD ALIGN="LEFT">1.0</TD>
<TD ALIGN="LEFT">1.0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Router Effort Multiplier</TD>
<TD ALIGN="LEFT">1.0</TD>
<TD ALIGN="LEFT">1.0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Optimize Hold Timing</TD>
<TD ALIGN="LEFT">IO Paths and Minimum TPD Paths</TD>
<TD ALIGN="LEFT">IO Paths and Minimum TPD Paths</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Optimize Fast-Corner Timing</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Optimize Timing</TD>
<TD ALIGN="LEFT">Normal compilation</TD>
<TD ALIGN="LEFT">Normal compilation</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Optimize IOC Register Placement for Timing</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Limit to One Fitting Attempt</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Final Placement Optimizations</TD>
<TD ALIGN="LEFT">Automatically</TD>
<TD ALIGN="LEFT">Automatically</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Fitter Aggressive Routability Optimizations</TD>
<TD ALIGN="LEFT">Automatically</TD>
<TD ALIGN="LEFT">Automatically</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Fitter Initial Placement Seed</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">1</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Slow Slew Rate</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">PCI I/O</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Weak Pull-Up Resistor</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Enable Bus-Hold Circuitry</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Global Memory Control Signals</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Packed Registers -- Stratix/Stratix GX</TD>
<TD ALIGN="LEFT">Auto</TD>
<TD ALIGN="LEFT">Auto</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Delay Chains</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Merge PLLs</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Perform Physical Synthesis for Combinational Logic</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Perform Register Duplication</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Perform Register Retiming</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Perform Asynchronous Signal Pipelining</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Fitter Effort</TD>
<TD ALIGN="LEFT">Auto Fit</TD>
<TD ALIGN="LEFT">Auto Fit</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Physical Synthesis Effort Level</TD>
<TD ALIGN="LEFT">Normal</TD>
<TD ALIGN="LEFT">Normal</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Logic Cell Insertion - Logic Duplication</TD>
<TD ALIGN="LEFT">Auto</TD>
<TD ALIGN="LEFT">Auto</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Register Duplication</TD>
<TD ALIGN="LEFT">Auto</TD>
<TD ALIGN="LEFT">Auto</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Global Clock</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Global Register Control Signals</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
</TABLE>
<P><A NAME="4"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Fitter Equations</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<a href="file:///D:/PLD/FPGAlicheng/music/we.fit.eqn.htm">Fitter Equations</a><BR>
<P><A NAME="5"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Pin-Out File</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<a href="file:///D:/PLD/FPGAlicheng/music/we.pin">Pin-Out File</a><BR>
<P><A NAME="6"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Fitter Resource Usage Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Resource</TH>
<TH>Usage</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total logic elements</TD>
<TD ALIGN="LEFT">20 / 10,570 ( < 1 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- Combinational with no register</TD>
<TD ALIGN="LEFT">12</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- Register only</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- Combinational with a register</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Logic element usage by number of LUT inputs</TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- 4 input functions</TD>
<TD ALIGN="LEFT">3</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- 3 input functions</TD>
<TD ALIGN="LEFT">7</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- 2 input functions</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- 1 input functions</TD>
<TD ALIGN="LEFT">1</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- 0 input functions</TD>
<TD ALIGN="LEFT">1</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Logic elements by mode</TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- normal mode</TD>
<TD ALIGN="LEFT">14</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- arithmetic mode</TD>
<TD ALIGN="LEFT">6</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- qfbk mode</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- register cascade mode</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- synchronous clear/load mode</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- asynchronous clear/load mode</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total LABs</TD>
<TD ALIGN="LEFT">4 / 1,057 ( < 1 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Logic elements in carry chains</TD>
<TD ALIGN="LEFT">7</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">User inserted logic elements </TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Virtual pins</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">I/O pins</TD>
<TD ALIGN="LEFT">8 / 336 ( 2 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- Clock pins </TD>
<TD ALIGN="LEFT">1 / 16 ( 6 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Global signals </TD>
<TD ALIGN="LEFT">3</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">M512s</TD>
<TD ALIGN="LEFT">0 / 94 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">M4Ks</TD>
<TD ALIGN="LEFT">1 / 60 ( 2 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">M-RAMs</TD>
<TD ALIGN="LEFT">0 / 1 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total memory bits</TD>
<TD ALIGN="LEFT">1,024 / 920,448 ( < 1 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total RAM block bits</TD>
<TD ALIGN="LEFT">4,608 / 920,448 ( < 1 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">DSP block 9-bit elements</TD>
<TD ALIGN="LEFT">0 / 48 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">PLLs</TD>
<TD ALIGN="LEFT">0 / 6 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Global clocks</TD>
<TD ALIGN="LEFT">3 / 16 ( 19 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Regional clocks</TD>
<TD ALIGN="LEFT">0 / 16 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Fast regional clocks</TD>
<TD ALIGN="LEFT">0 / 8 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">SERDES transmitters</TD>
<TD ALIGN="LEFT">0 / 44 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">SERDES receivers</TD>
<TD ALIGN="LEFT">0 / 44 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maximum fan-out node</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maximum fan-out</TD>
<TD ALIGN="LEFT">9</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Highest non-global fan-out signal</TD>
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