⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 we.tan.rpt.htm

📁 出血FPGA,用VHDL做的音乐盒
💻 HTM
📖 第 1 页 / 共 4 页
字号:
🔍
1234 
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">0.959 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[2]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[2]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">0.947 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[4]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[4]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">0.947 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[7]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[7]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">0.946 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[3]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[3]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">0.941 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[5]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[5]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">0.846 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[6]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[6]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">0.844 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[1]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[1]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">0.843 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[0]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[0]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">0.626 ns</TD>
</TR>
</TABLE>
<P><A NAME="6"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Clock Hold: 'CLK8Hz'</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Minimum Slack</TH>
<TH>From</TH>
<TH>To</TH>
<TH>From Clock</TH>
<TH>To Clock</TH>
<TH>Required Hold Relationship</TH>
<TH>Required Shortest P2P Time</TH>
<TH>Actual Shortest P2P Time</TH>
</TR>
<TR valign="middle" style="color: RED">
<TD ALIGN="LEFT">Not operational: Clock Skew > Data Delay</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]</TD>
<TD ALIGN="LEFT">TONETABA:inst2|HIGH</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.265 ns</TD>
</TR>
<TR valign="middle" style="color: RED">
<TD ALIGN="LEFT">Not operational: Clock Skew > Data Delay</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[0]</TD>
<TD ALIGN="LEFT">TONETABA:inst2|CODE[1]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.559 ns</TD>
</TR>
<TR valign="middle" style="color: RED">
<TD ALIGN="LEFT">Not operational: Clock Skew > Data Delay</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[1]</TD>
<TD ALIGN="LEFT">TONETABA:inst2|CODE[1]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.663 ns</TD>
</TR>
<TR valign="middle" style="color: RED">
<TD ALIGN="LEFT">Not operational: Clock Skew > Data Delay</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[0]</TD>
<TD ALIGN="LEFT">TONETABA:inst2|CODE[0]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.735 ns</TD>
</TR>
<TR valign="middle" style="color: RED">
<TD ALIGN="LEFT">Not operational: Clock Skew > Data Delay</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]</TD>
<TD ALIGN="LEFT">TONETABA:inst2|CODE[1]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.775 ns</TD>
</TR>
<TR valign="middle" style="color: RED">
<TD ALIGN="LEFT">Not operational: Clock Skew > Data Delay</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[1]</TD>
<TD ALIGN="LEFT">TONETABA:inst2|CODE[0]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.839 ns</TD>
</TR>
<TR valign="middle" style="color: RED">
<TD ALIGN="LEFT">Not operational: Clock Skew > Data Delay</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[1]</TD>
<TD ALIGN="LEFT">TONETABA:inst2|CODE[2]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.841 ns</TD>
</TR>
<TR valign="middle" style="color: RED">
<TD ALIGN="LEFT">Not operational: Clock Skew > Data Delay</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]</TD>
<TD ALIGN="LEFT">TONETABA:inst2|CODE[2]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.955 ns</TD>
</TR>
<TR valign="middle" style="color: RED">
<TD ALIGN="LEFT">Not operational: Clock Skew > Data Delay</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]</TD>
<TD ALIGN="LEFT">TONETABA:inst2|CODE[0]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.961 ns</TD>
</TR>
<TR valign="middle" style="color: RED">
<TD ALIGN="LEFT">Not operational: Clock Skew > Data Delay</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2]</TD>
<TD ALIGN="LEFT">TONETABA:inst2|CODE[2]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">2.793 ns</TD>
</TR>
</TABLE>
<P><A NAME="7"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>tco</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Slack</TH>
<TH>Required tco</TH>
<TH>Actual tco</TH>
<TH>From</TH>
<TH>To</TH>
<TH>From Clock</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">13.040 ns</TD>
<TD ALIGN="LEFT">TONETABA:inst2|CODE[2]</TD>
<TD ALIGN="LEFT">CODE[2]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">12.984 ns</TD>
<TD ALIGN="LEFT">TONETABA:inst2|HIGH</TD>
<TD ALIGN="LEFT">HIGN</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">12.696 ns</TD>
<TD ALIGN="LEFT">TONETABA:inst2|CODE[0]</TD>
<TD ALIGN="LEFT">CODE[0]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">12.396 ns</TD>
<TD ALIGN="LEFT">TONETABA:inst2|CODE[1]</TD>
<TD ALIGN="LEFT">CODE[1]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
</TR>
</TABLE>
<P><A NAME="8"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Timing Analyzer Messages</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<PRE>
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Sep 23 20:22:06 2008
Info: Command: quartus_tan --lower_priority --read_settings_files=off --write_settings_files=off we -c we --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "TONETABA:inst2|HIGH" is a latch
    Warning: Node "TONETABA:inst2|CODE[2]" is a latch
    Warning: Node "TONETABA:inst2|CODE[1]" is a latch
    Warning: Node "TONETABA:inst2|CODE[0]" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK8Hz" is an undefined clock
Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "TONETABA:inst2|Mux4~31" as buffer
    Info: Detected ripple clock "lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[0]" as buffer
    Info: Detected ripple clock "lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[1]" as buffer
    Info: Detected ripple clock "lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2]" as buffer
    Info: Detected ripple clock "lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]" as buffer
Info: Clock "CLK8Hz" has Internal fmax of 290.87 MHz between source memory "lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0" and destination memory "lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]" (period= 3.438 ns)
    Info: + Longest memory to memory delay is 2.875 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X37_Y23; Fanout = 4; MEM Node = 'lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0'
        Info: 2: + IC(0.000 ns) + CELL(2.875 ns) = 2.875 ns; Loc. = M4K_X37_Y23; Fanout = 5; MEM Node = 'lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]'
        Info: Total cell delay = 2.875 ns ( 100.00 % )
    Info: - Smallest clock skew is -0.012 ns
        Info: + Shortest clock path from clock "CLK8Hz" to destination memory is 2.861 ns
            Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 20; CLK Node = 'CLK8Hz'
            Info: 2: + IC(1.533 ns) + CELL(0.500 ns) = 2.861 ns; Loc. = M4K_X37_Y23; Fanout = 5; MEM Node = 'lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]'
            Info: Total cell delay = 1.328 ns ( 46.42 % )
            Info: Total interconnect delay = 1.533 ns ( 53.58 % )
        Info: - Longest clock path from clock "CLK8Hz" to source memory is 2.873 ns
            Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 20; CLK Node = 'CLK8Hz'
            Info: 2: + IC(1.533 ns) + CELL(0.512 ns) = 2.873 ns; Loc. = M4K_X37_Y23; Fanout = 4; MEM Node = 'lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0'
            Info: Total cell delay = 1.340 ns ( 46.64 % )
            Info: Total interconnect delay = 1.533 ns ( 53.36 % )
    Info: + Micro clock to output delay of source is 0.420 ns
    Info: + Micro setup delay of destination is 0.131 ns
Warning: Circuit may not operate. Detected 10 non-operational path(s) clocked by clock "CLK8Hz" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]" and destination pin or register "TONETABA:inst2|HIGH" for clock "CLK8Hz" (Hold time is 4.193 ns)
    Info: + Largest clock skew is 5.878 ns
        Info: + Longest clock path from clock "CLK8Hz" to destination register is 8.739 ns
            Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 20; CLK Node = 'CLK8Hz'
            Info: 2: + IC(1.533 ns) + CELL(0.991 ns) = 3.352 ns; Loc. = M4K_X37_Y23; Fanout = 2; MEM Node = 'lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2]'
            Info: 3: + IC(0.782 ns) + CELL(0.366 ns) = 4.500 ns; Loc. = LC_X39_Y23_N4; Fanout = 4; COMB Node = 'TONETABA:inst2|Mux4~31'
            Info: 4: + IC(4.164 ns) + CELL(0.075 ns) = 8.739 ns; Loc. = LC_X39_Y23_N1; Fanout = 1; REG Node = 'TONETABA:inst2|HIGH'
            Info: Total cell delay = 2.260 ns ( 25.86 % )
            Info: Total interconnect delay = 6.479 ns ( 74.14 % )
        Info: - Shortest clock path from clock "CLK8Hz" to source memory is 2.861 ns
            Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 20; CLK Node = 'CLK8Hz'
            Info: 2: + IC(1.533 ns) + CELL(0.500 ns) = 2.861 ns; Loc. = M4K_X37_Y23; Fanout = 5; MEM Node = 'lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]'
            Info: Total cell delay = 1.328 ns ( 46.42 % )
            Info: Total interconnect delay = 1.533 ns ( 53.58 % )
    Info: - Micro clock to output delay of source is 0.420 ns
    Info: - Shortest memory to register delay is 1.265 ns
        Info: 1: + IC(0.000 ns) + CELL(0.071 ns) = 0.071 ns; Loc. = M4K_X37_Y23; Fanout = 5; MEM Node = 'lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]'
        Info: 2: + IC(0.828 ns) + CELL(0.366 ns) = 1.265 ns; Loc. = LC_X39_Y23_N1; Fanout = 1; REG Node = 'TONETABA:inst2|HIGH'
        Info: Total cell delay = 0.437 ns ( 34.55 % )
        Info: Total interconnect delay = 0.828 ns ( 65.45 % )
    Info: + Micro hold delay of destination is 0.000 ns
Info: tco from clock "CLK8Hz" to destination pin "CODE[2]" through register "TONETABA:inst2|CODE[2]" is 13.040 ns
    Info: + Longest clock path from clock "CLK8Hz" to source register is 8.738 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 20; CLK Node = 'CLK8Hz'
        Info: 2: + IC(1.533 ns) + CELL(0.991 ns) = 3.352 ns; Loc. = M4K_X37_Y23; Fanout = 2; MEM Node = 'lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2]'
        Info: 3: + IC(0.782 ns) + CELL(0.366 ns) = 4.500 ns; Loc. = LC_X39_Y23_N4; Fanout = 4; COMB Node = 'TONETABA:inst2|Mux4~31'
        Info: 4: + IC(4.163 ns) + CELL(0.075 ns) = 8.738 ns; Loc. = LC_X39_Y23_N3; Fanout = 1; REG Node = 'TONETABA:inst2|CODE[2]'
        Info: Total cell delay = 2.260 ns ( 25.86 % )
        Info: Total interconnect delay = 6.478 ns ( 74.14 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 4.302 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X39_Y23_N3; Fanout = 1; REG Node = 'TONETABA:inst2|CODE[2]'
        Info: 2: + IC(1.898 ns) + CELL(2.404 ns) = 4.302 ns; Loc. = PIN_U9; Fanout = 0; PIN Node = 'CODE[2]'
        Info: Total cell delay = 2.404 ns ( 55.88 % )
        Info: Total interconnect delay = 1.898 ns ( 44.12 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 8 warnings
    Info: Processing ended: Tue Sep 23 20:22:06 2008
    Info: Elapsed time: 00:00:01
</PRE>
<HR>

<A HREF="#top">Top</A>

</BODY>

</HTML>
1234

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -