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📁 出血FPGA,用VHDL做的音乐盒
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1234 
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[2]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[6]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.617 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[2]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[7]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.617 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[1]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[5]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.553 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[3]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[5]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.553 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[1]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[6]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.553 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[3]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[6]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.553 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[1]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[7]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.553 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[3]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[7]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.553 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[4]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[5]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.510 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[4]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[6]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.510 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[4]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[7]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.510 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[0]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[4]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.488 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[0]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[3]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.428 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[2]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[4]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.416 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[0]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[2]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.368 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[2]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[3]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.356 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[3]</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg3</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.200 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[3]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[4]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.350 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[2]</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg2</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.195 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[6]</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg6</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.194 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[0]</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg0</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.193 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[1]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[4]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.343 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[5]</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg5</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.186 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[4]</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg4</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.184 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[7]</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg7</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.176 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[1]</TD>
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ram_block1a3~porta_address_reg1</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.174 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[5]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[7]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.286 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[1]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[3]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.283 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[5]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[6]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.226 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[6]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[7]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.224 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[1]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[2]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">1.223 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">Restricted to 422.12 MHz ( period = 2.369 ns )</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[0]</TD>
<TD ALIGN="LEFT">NoteTabs:inst3|Counter[1]</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
1234

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