we.cmp.rpt

出血FPGA,用VHDL做的音乐盒

Type           : Untyped

Parameter Name : OUTDATA_ACLR_A
Value          : NONE
Type           : Untyped

Parameter Name : WRCONTROL_ACLR_A
Value          : NONE
Type           : Untyped

Parameter Name : INDATA_ACLR_A
Value          : NONE
Type           : Untyped

Parameter Name : BYTEENA_ACLR_A
Value          : NONE
Type           : Untyped

Parameter Name : WIDTH_B
Value          : 1
Type           : Untyped

Parameter Name : WIDTHAD_B
Value          : 1
Type           : Untyped

Parameter Name : NUMWORDS_B
Value          : 1
Type           : Untyped

Parameter Name : INDATA_REG_B
Value          : CLOCK1
Type           : Untyped

Parameter Name : WRCONTROL_WRADDRESS_REG_B
Value          : CLOCK1
Type           : Untyped

Parameter Name : RDCONTROL_REG_B
Value          : CLOCK1
Type           : Untyped

Parameter Name : ADDRESS_REG_B
Value          : CLOCK1
Type           : Untyped

Parameter Name : OUTDATA_REG_B
Value          : UNREGISTERED
Type           : Untyped

Parameter Name : BYTEENA_REG_B
Value          : CLOCK1
Type           : Untyped

Parameter Name : INDATA_ACLR_B
Value          : NONE
Type           : Untyped

Parameter Name : WRCONTROL_ACLR_B
Value          : NONE
Type           : Untyped

Parameter Name : ADDRESS_ACLR_B
Value          : NONE
Type           : Untyped

Parameter Name : OUTDATA_ACLR_B
Value          : NONE
Type           : Untyped

Parameter Name : RDCONTROL_ACLR_B
Value          : NONE
Type           : Untyped

Parameter Name : BYTEENA_ACLR_B
Value          : NONE
Type           : Untyped

Parameter Name : WIDTH_BYTEENA_A
Value          : 1
Type           : Untyped

Parameter Name : WIDTH_BYTEENA_B
Value          : 1
Type           : Untyped

Parameter Name : RAM_BLOCK_TYPE
Value          : AUTO
Type           : Untyped

Parameter Name : BYTE_SIZE
Value          : 8
Type           : Untyped

Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS
Value          : DONT_CARE
Type           : Untyped

Parameter Name : INIT_FILE
Value          : YINYUE.mif
Type           : Untyped

Parameter Name : INIT_FILE_LAYOUT
Value          : PORT_A
Type           : Untyped

Parameter Name : MAXIMUM_DEPTH
Value          : 0
Type           : Untyped

Parameter Name : CLOCK_ENABLE_INPUT_A
Value          : NORMAL
Type           : Untyped

Parameter Name : CLOCK_ENABLE_INPUT_B
Value          : NORMAL
Type           : Untyped

Parameter Name : CLOCK_ENABLE_OUTPUT_A
Value          : NORMAL
Type           : Untyped

Parameter Name : CLOCK_ENABLE_OUTPUT_B
Value          : NORMAL
Type           : Untyped

Parameter Name : DEVICE_FAMILY
Value          : Stratix
Type           : Untyped

Parameter Name : CBXI_PARAMETER
Value          : altsyncram_f431
Type           : Untyped
+--------------------------------------------------------------------------------+

Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/PLD/FPGAlicheng/music/we.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Sep 23 20:21:50 2008
Info: Command: quartus_map --lower_priority --read_settings_files=on --write_settings_files=off we -c we
Info: Found 2 design units, including 1 entities, in source file SHUKONGDIV.vhd
    Info: Found design unit 1: SHUKONG_DIV-MA
    Info: Found entity 1: SHUKONG_DIV
Info: Found 2 design units, including 1 entities, in source file SPEAKER.vhd
    Info: Found design unit 1: SPEAKER-MA
    Info: Found entity 1: SPEAKER
Info: Found 1 design units, including 1 entities, in source file we.bdf
    Info: Found entity 1: we
Info: Found 2 design units, including 1 entities, in source file TONETABA.vhd
    Info: Found design unit 1: TONETABA-MA
    Info: Found entity 1: TONETABA
Info: Found 2 design units, including 1 entities, in source file NoteTabs.vhd
    Info: Found design unit 1: NoteTabs-one
    Info: Found entity 1: NoteTabs
Warning: Can't analyze file -- file D:/PLD/FPGAlicheng/music/lpm_rom1.tdf is missing
Info: Found 1 design units, including 1 entities, in source file lpm_rom0.tdf
    Info: Found entity 1: lpm_rom0
Info: Elaborating entity "we" for the top level hierarchy
Info: Elaborating entity "TONETABA" for hierarchy "TONETABA:inst2"
Warning (10631): VHDL Process Statement warning at TONETABA.vhd(12): inferring latch(es) for signal or variable "TONE", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at TONETABA.vhd(12): inferring latch(es) for signal or variable "CODE", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at TONETABA.vhd(12): inferring latch(es) for signal or variable "HIGH", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "HIGH"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "CODE[0]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "CODE[1]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "CODE[2]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "CODE[3]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[0]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[1]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[2]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[3]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[4]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[5]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[6]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[7]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[8]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[9]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[10]"
Info: Elaborating entity "lpm_rom0" for hierarchy "lpm_rom0:inst"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "lpm_rom0:inst|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "lpm_rom0:inst|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_f431.tdf
    Info: Found entity 1: altsyncram_f431
Info: Elaborating entity "altsyncram_f431" for hierarchy "lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated"
Info: Elaborating entity "NoteTabs" for hierarchy "NoteTabs:inst3"
Info: Elaborating entity "SPEAKER" for hierarchy "SPEAKER:inst1"
Warning (10036): Verilog HDL or VHDL warning at SPEAKER.vhd(10): object "FULLSPKS" assigned a value but never read
Warning (10034): Output port "SPKS" at SPEAKER.vhd(7) has no driver
Warning: Entity "SPEAKER" contains only dangling pins
Warning: Latch TONETABA:inst2|HIGH has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]
Warning: Latch TONETABA:inst2|CODE[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2]
Warning: Latch TONETABA:inst2|CODE[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[1]
Warning: Latch TONETABA:inst2|CODE[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[0]
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "SPKS" stuck at GND
    Warning: Pin "CODE[3]" stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "CLK12M"
Info: Implemented 31 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 6 output pins
    Info: Implemented 19 logic cells
    Info: Implemented 4 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings
    Info: Processing ended: Tue Sep 23 20:21:51 2008
    Info: Elapsed time: 00:00:02


+---------------------------------------------------------------------+
; Fitter Summary                                                      ;
+--------------------------+------------------------------------------+
; Fitter Status            ; Successful - Tue Sep 23 20:21:59 2008    ;
; Quartus II Version       ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name            ; we                                       ;
; Top-level Entity Name    ; we                                       ;
; Family                   ; Stratix                                  ;
; Device                   ; EP1S10F484C5                             ;
; Timing Models            ; Final                                    ;
; Total logic elements     ; 20 / 10,570 ( < 1 % )                    ;
; Total pins               ; 8 / 336 ( 2 % )                          ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 1,024 / 920,448 ( < 1 % )                ;
; DSP block 9-bit elements ; 0 / 48 ( 0 % )                           ;
; Total PLLs               ; 0 / 6 ( 0 % )                            ;
; Total DLLs               ; 0 / 2 ( 0 % )                            ;
+--------------------------+------------------------------------------+


+--------------------------------------------------------------------------------+
; Fitter Settings                                                                ;
+--------------------------------------------------------------------------------+
Option        : Device
Setting       : AUTO
Default Value : 

Option        : Use smart compilation
Setting       : Off
Default Value : Off

Option        : Router Timing Optimization Level
Setting       : Normal
Default Value : Normal

Option        : Placement Effort Multiplier
Setting       : 1.0
Default Value : 1.0

Option        : Router Effort Multiplier
Setting       : 1.0
Default Value : 1.0

Option        : Optimize Hold Timing
Setting       : IO Paths and Minimum TPD Paths
Default Value : IO Paths and Minimum TPD Paths

Option        : Optimize Fast-Corner Timing
Setting       : Off
Default Value : Off

Option        : Optimize Timing
Setting       : Normal compilation
Default Value : Normal compilation

Option        : Optimize IOC Register Placement for Timing
Setting       : On
Default Value : On

Option        : Limit to One Fitting Attempt
Setting       : Off
Default Value : Off

Option        : Final Placement Optimizations
Setting       : Automatically
Default Value : Automatically

Option        : Fitter Aggressive Routability Optimizations
Setting       : Automatically
Default Value : Automatically

Option        : Fitter Initial Placement Seed
Setting       : 1
Default Value : 1

Option        : Slow Slew Rate
Setting       : Off
Default Value : Off

Option        : PCI I/O
Setting       : Off
Default Value : Off

Option        : Weak Pull-Up Resistor
Setting       : Off
Default Value : Off

Option        : Enable Bus-Hold Circuitry
Setting       : Off
Default Value : Off

Option        : Auto Global Memory Control Signals
Setting       : Off
Default Value : Off

Option        : Auto Packed Registers -- Stratix/Stratix GX
Setting       : Auto
Default Value : Auto

Option        : Auto Delay Chains
Setting       : On
Default Value : On

Option        : Auto Merge PLLs
Setting       : On
Default Value : On

Option        : Perform Physical Synthesis for Combinational Logic
Setting       : Off
Default Value : Off

Option        : Perform Register Duplication
Setting       : Off
Default Value : Off

Option        : Perform Register Retiming
Setting       : Off
Default Value : Off

Option        : Perform Asynchronous Signal Pipelining
Setting       : Off
Default Value : Off

Option        : Fitter Effort
Setting       : Auto Fit
Default Value : Auto Fit

Option        : Physical Synthesis Effort Level
Setting       : Normal
Default Value : Normal

Option        : Logic Cell Insertion - Logic Duplication
Setting       : Auto
Default Value : Auto

Option        : Auto Register Duplication
Setting       : Auto
Default Value : Auto

Option        : Auto Global Clock
Setting       : On
Default Value : On

Option        : Auto Global Register Control Signals
Setting       : On
Default Value : On
+--------------------------------------------------------------------------------+



+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in D:/PLD/FPGAlicheng/music/we.fit.eqn.


+--------------+