we.cmp.rpt

出血FPGA,用VHDL做的音乐盒

Compilation report for we
Tue Sep 23 20:22:06 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow Log
  7. Analysis & Synthesis Summary
  8. Analysis & Synthesis Settings
  9. Analysis & Synthesis Source Files Read
 10. Analysis & Synthesis Resource Usage Summary
 11. Analysis & Synthesis Resource Utilization by Entity
 12. Analysis & Synthesis RAM Summary
 13. User-Specified and Inferred Latches
 14. General Register Statistics
 15. Source assignments for lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated
 16. Parameter Settings for User Entity Instance: lpm_rom0:inst|altsyncram:altsyncram_component
 17. Analysis & Synthesis Equations
 18. Analysis & Synthesis Messages
 19. Fitter Summary
 20. Fitter Settings
 21. Fitter Equations
 22. Pin-Out File
 23. Fitter Resource Usage Summary
 24. Input Pins
 25. Output Pins
 26. I/O Bank Usage
 27. All Package Pins
 28. Output Pin Default Load For Reported TCO
 29. Fitter Resource Utilization by Entity
 30. Delay Chain Summary
 31. Pad To Core Delay Chain Fanout
 32. Control Signals
 33. Global & Other Fast Signals
 34. Non-Global High Fan-Out Signals
 35. Fitter RAM Summary
 36. Interconnect Usage Summary
 37. LAB Logic Elements
 38. LAB-wide Signals
 39. LAB Signals Sourced
 40. LAB Signals Sourced Out
 41. LAB Distinct Inputs
 42. Fitter Device Options
 43. Advanced Data - General
 44. Advanced Data - Placement Preparation
 45. Advanced Data - Placement
 46. Advanced Data - Routing
 47. Fitter Messages
 48. Fitter Suppressed Messages
 49. Assembler Summary
 50. Assembler Settings
 51. Assembler Generated Files
 52. Assembler Device Options: D:/PLD/FPGAlicheng/music/we.sof
 53. Assembler Device Options: D:/PLD/FPGAlicheng/music/we.pof
 54. Assembler Messages
 55. Timing Analyzer Summary
 56. Timing Analyzer Settings
 57. Clock Settings Summary
 58. Clock Setup: 'CLK8Hz'
 59. Clock Hold: 'CLK8Hz'
 60. tco
 61. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------+
; Flow Summary                                                        ;
+--------------------------+------------------------------------------+
; Flow Status              ; Successful - Tue Sep 23 20:22:06 2008    ;
; Quartus II Version       ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name            ; we                                       ;
; Top-level Entity Name    ; we                                       ;
; Family                   ; Stratix                                  ;
; Met timing requirements  ; No                                       ;
; Total logic elements     ; 20 / 10,570 ( < 1 % )                    ;
; Total pins               ; 8 / 336 ( 2 % )                          ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 1,024 / 920,448 ( < 1 % )                ;
; DSP block 9-bit elements ; 0 / 48 ( 0 % )                           ;
; Total PLLs               ; 0 / 6 ( 0 % )                            ;
; Total DLLs               ; 0 / 2 ( 0 % )                            ;
; Device                   ; EP1S10F484C5                             ;
; Timing Models            ; Final                                    ;
+--------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 09/23/2008 20:21:50 ;
; Main task         ; Compilation         ;
; Revision Name     ; we                  ;
+-------------------+---------------------+


+--------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                               ;
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+



+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:02     ;
; Fitter               ; 00:00:06     ;
; Assembler            ; 00:00:03     ;
; Timing Analyzer      ; 00:00:01     ;
; Total                ; 00:00:12     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --lower_priority --read_settings_files=on --write_settings_files=off we -c we
quartus_fit --lower_priority --read_settings_files=off --write_settings_files=off we -c we
quartus_asm --lower_priority --read_settings_files=off --write_settings_files=off we -c we
quartus_tan --lower_priority --read_settings_files=off --write_settings_files=off we -c we --timing_analysis_only



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Sep 23 20:21:51 2008    ;
; Quartus II Version          ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name               ; we                                       ;
; Top-level Entity Name       ; we                                       ;
; Family                      ; Stratix                                  ;
; Total logic elements        ; 19                                       ;
; Total pins                  ; 8                                        ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 1,024                                    ;
; DSP block 9-bit elements    ; 0                                        ;
; Total PLLs                  ; 0                                        ;
; Total DLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                  ;
+--------------------------------------------------------------------------------+
Option        : Top-level entity name
Setting       : we
Default Value : we

Option        : Family name
Setting       : Stratix
Default Value : Stratix

Option        : Use smart compilation
Setting       : Off
Default Value : Off

Option        : Restructure Multiplexers
Setting       : Auto
Default Value : Auto

Option        : Create Debugging Nodes for IP Cores
Setting       : Off
Default Value : Off

Option        : Preserve fewer node names
Setting       : On
Default Value : On

Option        : Disable OpenCore Plus hardware evaluation
Setting       : Off
Default Value : Off

Option        : Verilog Version
Setting       : Verilog_2001
Default Value : Verilog_2001

Option        : VHDL Version
Setting       : VHDL93
Default Value : VHDL93

Option        : State Machine Processing
Setting       : Auto
Default Value : Auto

Option        : Extract Verilog State Machines
Setting       : On
Default Value : On

Option        : Extract VHDL State Machines
Setting       : On
Default Value : On

Option        : Add Pass-Through Logic to Inferred RAMs
Setting       : On
Default Value : On

Option        : DSP Block Balancing
Setting       : Auto
Default Value : Auto

Option        : Maximum DSP Block Usage
Setting       : Unlimited
Default Value : Unlimited

Option        : NOT Gate Push-Back
Setting       : On
Default Value : On

Option        : Power-Up Don't Care
Setting       : On
Default Value : On

Option        : Remove Redundant Logic Cells
Setting       : Off
Default Value : Off

Option        : Remove Duplicate Registers
Setting       : On
Default Value : On

Option        : Ignore CARRY Buffers
Setting       : Off
Default Value : Off

Option        : Ignore CASCADE Buffers
Setting       : Off
Default Value : Off

Option        : Ignore GLOBAL Buffers
Setting       : Off
Default Value : Off

Option        : Ignore ROW GLOBAL Buffers
Setting       : Off
Default Value : Off

Option        : Ignore LCELL Buffers
Setting       : Off
Default Value : Off

Option        : Ignore SOFT Buffers
Setting       : On
Default Value : On

Option        : Limit AHDL Integers to 32 Bits
Setting       : Off
Default Value : Off

Option        : Optimization Technique -- Stratix/Stratix GX
Setting       : Balanced
Default Value : Balanced

Option        : Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II
Setting       : 70
Default Value : 70

Option        : Auto Carry Chains
Setting       : On
Default Value : On

Option        : Auto Open-Drain Pins
Setting       : On
Default Value : On

Option        : Remove Duplicate Logic
Setting       : On
Default Value : On

Option        : Perform WYSIWYG Primitive Resynthesis
Setting       : Off
Default Value : Off

Option        : Perform gate-level register retiming
Setting       : Off
Default Value : Off

Option        : Allow register retiming to trade off Tsu/Tco with Fmax
Setting       : On
Default Value : On

Option        : Auto ROM Replacement
Setting       : On
Default Value : On

Option        : Auto RAM Replacement
Setting       : On
Default Value : On

Option        : Auto DSP Block Replacement
Setting       : On
Default Value : On

Option        : Auto Shift Register Replacement
Setting       : On
Default Value : On

Option        : Auto Clock Enable Replacement
Setting       : On
Default Value : On

Option        : Allow Synchronous Control Signals
Setting       : On
Default Value : On

Option        : Force Use of Synchronous Clear Signals
Setting       : Off
Default Value : Off

Option        : Auto RAM Block Balancing
Setting       : On
Default Value : On

Option        : Auto Resource Sharing
Setting       : Off
Default Value : Off

Option        : Allow Any RAM Size For Recognition
Setting       : Off
Default Value : Off

Option        : Allow Any ROM Size For Recognition
Setting       : Off
Default Value : Off

Option        : Allow Any Shift Register Size For Recognition
Setting       : Off
Default Value : Off

Option        : Maximum Number of M512 Memory Blocks
Setting       : Unlimited
Default Value : Unlimited

Option        : Maximum Number of M4K Memory Blocks
Setting       : Unlimited
Default Value : Unlimited

Option        : Maximum Number of M-RAM Memory Blocks
Setting       : Unlimited
Default Value : Unlimited

Option        : Ignore translate_off and translate_on Synthesis Directives
Setting       : Off
Default Value : Off

Option        : Show Parameter Settings Tables in Synthesis Report
Setting       : On
Default Value : On

Option        : Ignore Maximum Fan-Out Assignments
Setting       : Off
Default Value : Off

Option        : Retiming Meta-Stability Register Sequence Length