we.map.rpt

出血FPGA,用VHDL做的音乐盒

; Total registers                              ; 8     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 8     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------+
; Source assignments for lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated ;
+--------------------------------------------------------------------------------+
Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS
Value      : NORMAL_COMPILATION
From       : -
To         : -
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_rom0:inst|altsyncram:altsyncram_component ;
+--------------------------------------------------------------------------------+
Parameter Name : BYTE_SIZE_BLOCK
Value          : 8
Type           : Untyped

Parameter Name : AUTO_CARRY_CHAINS
Value          : ON
Type           : AUTO_CARRY

Parameter Name : IGNORE_CARRY_BUFFERS
Value          : OFF
Type           : IGNORE_CARRY

Parameter Name : AUTO_CASCADE_CHAINS
Value          : ON
Type           : AUTO_CASCADE

Parameter Name : IGNORE_CASCADE_BUFFERS
Value          : OFF
Type           : IGNORE_CASCADE

Parameter Name : OPERATION_MODE
Value          : ROM
Type           : Untyped

Parameter Name : WIDTH_A
Value          : 4
Type           : Untyped

Parameter Name : WIDTHAD_A
Value          : 8
Type           : Untyped

Parameter Name : NUMWORDS_A
Value          : 256
Type           : Untyped

Parameter Name : OUTDATA_REG_A
Value          : CLOCK0
Type           : Untyped

Parameter Name : ADDRESS_ACLR_A
Value          : NONE
Type           : Untyped

Parameter Name : OUTDATA_ACLR_A
Value          : NONE
Type           : Untyped

Parameter Name : WRCONTROL_ACLR_A
Value          : NONE
Type           : Untyped

Parameter Name : INDATA_ACLR_A
Value          : NONE
Type           : Untyped

Parameter Name : BYTEENA_ACLR_A
Value          : NONE
Type           : Untyped

Parameter Name : WIDTH_B
Value          : 1
Type           : Untyped

Parameter Name : WIDTHAD_B
Value          : 1
Type           : Untyped

Parameter Name : NUMWORDS_B
Value          : 1
Type           : Untyped

Parameter Name : INDATA_REG_B
Value          : CLOCK1
Type           : Untyped

Parameter Name : WRCONTROL_WRADDRESS_REG_B
Value          : CLOCK1
Type           : Untyped

Parameter Name : RDCONTROL_REG_B
Value          : CLOCK1
Type           : Untyped

Parameter Name : ADDRESS_REG_B
Value          : CLOCK1
Type           : Untyped

Parameter Name : OUTDATA_REG_B
Value          : UNREGISTERED
Type           : Untyped

Parameter Name : BYTEENA_REG_B
Value          : CLOCK1
Type           : Untyped

Parameter Name : INDATA_ACLR_B
Value          : NONE
Type           : Untyped

Parameter Name : WRCONTROL_ACLR_B
Value          : NONE
Type           : Untyped

Parameter Name : ADDRESS_ACLR_B
Value          : NONE
Type           : Untyped

Parameter Name : OUTDATA_ACLR_B
Value          : NONE
Type           : Untyped

Parameter Name : RDCONTROL_ACLR_B
Value          : NONE
Type           : Untyped

Parameter Name : BYTEENA_ACLR_B
Value          : NONE
Type           : Untyped

Parameter Name : WIDTH_BYTEENA_A
Value          : 1
Type           : Untyped

Parameter Name : WIDTH_BYTEENA_B
Value          : 1
Type           : Untyped

Parameter Name : RAM_BLOCK_TYPE
Value          : AUTO
Type           : Untyped

Parameter Name : BYTE_SIZE
Value          : 8
Type           : Untyped

Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS
Value          : DONT_CARE
Type           : Untyped

Parameter Name : INIT_FILE
Value          : YINYUE.mif
Type           : Untyped

Parameter Name : INIT_FILE_LAYOUT
Value          : PORT_A
Type           : Untyped

Parameter Name : MAXIMUM_DEPTH
Value          : 0
Type           : Untyped

Parameter Name : CLOCK_ENABLE_INPUT_A
Value          : NORMAL
Type           : Untyped

Parameter Name : CLOCK_ENABLE_INPUT_B
Value          : NORMAL
Type           : Untyped

Parameter Name : CLOCK_ENABLE_OUTPUT_A
Value          : NORMAL
Type           : Untyped

Parameter Name : CLOCK_ENABLE_OUTPUT_B
Value          : NORMAL
Type           : Untyped

Parameter Name : DEVICE_FAMILY
Value          : Stratix
Type           : Untyped

Parameter Name : CBXI_PARAMETER
Value          : altsyncram_f431
Type           : Untyped
+--------------------------------------------------------------------------------+

Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/PLD/FPGAlicheng/music/we.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Sep 23 20:21:50 2008
Info: Command: quartus_map --lower_priority --read_settings_files=on --write_settings_files=off we -c we
Info: Found 2 design units, including 1 entities, in source file SHUKONGDIV.vhd
    Info: Found design unit 1: SHUKONG_DIV-MA
    Info: Found entity 1: SHUKONG_DIV
Info: Found 2 design units, including 1 entities, in source file SPEAKER.vhd
    Info: Found design unit 1: SPEAKER-MA
    Info: Found entity 1: SPEAKER
Info: Found 1 design units, including 1 entities, in source file we.bdf
    Info: Found entity 1: we
Info: Found 2 design units, including 1 entities, in source file TONETABA.vhd
    Info: Found design unit 1: TONETABA-MA
    Info: Found entity 1: TONETABA
Info: Found 2 design units, including 1 entities, in source file NoteTabs.vhd
    Info: Found design unit 1: NoteTabs-one
    Info: Found entity 1: NoteTabs
Warning: Can't analyze file -- file D:/PLD/FPGAlicheng/music/lpm_rom1.tdf is missing
Info: Found 1 design units, including 1 entities, in source file lpm_rom0.tdf
    Info: Found entity 1: lpm_rom0
Info: Elaborating entity "we" for the top level hierarchy
Info: Elaborating entity "TONETABA" for hierarchy "TONETABA:inst2"
Warning (10631): VHDL Process Statement warning at TONETABA.vhd(12): inferring latch(es) for signal or variable "TONE", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at TONETABA.vhd(12): inferring latch(es) for signal or variable "CODE", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at TONETABA.vhd(12): inferring latch(es) for signal or variable "HIGH", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "HIGH"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "CODE[0]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "CODE[1]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "CODE[2]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "CODE[3]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[0]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[1]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[2]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[3]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[4]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[5]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[6]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[7]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[8]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[9]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[10]"
Info: Elaborating entity "lpm_rom0" for hierarchy "lpm_rom0:inst"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "lpm_rom0:inst|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "lpm_rom0:inst|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_f431.tdf
    Info: Found entity 1: altsyncram_f431
Info: Elaborating entity "altsyncram_f431" for hierarchy "lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated"
Info: Elaborating entity "NoteTabs" for hierarchy "NoteTabs:inst3"
Info: Elaborating entity "SPEAKER" for hierarchy "SPEAKER:inst1"
Warning (10036): Verilog HDL or VHDL warning at SPEAKER.vhd(10): object "FULLSPKS" assigned a value but never read
Warning (10034): Output port "SPKS" at SPEAKER.vhd(7) has no driver
Warning: Entity "SPEAKER" contains only dangling pins
Warning: Latch TONETABA:inst2|HIGH has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]
Warning: Latch TONETABA:inst2|CODE[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2]
Warning: Latch TONETABA:inst2|CODE[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[1]
Warning: Latch TONETABA:inst2|CODE[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[0]
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "SPKS" stuck at GND
    Warning: Pin "CODE[3]" stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "CLK12M"
Info: Implemented 31 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 6 output pins
    Info: Implemented 19 logic cells
    Info: Implemented 4 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings
    Info: Processing ended: Tue Sep 23 20:21:51 2008
    Info: Elapsed time: 00:00:02