📄 we.map.rpt
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File Name with User-Entered Path : we.bdf
Used in Netlist : yes
File Type : User Block Diagram/Schematic File
File Name with Absolute Path : D:/PLD/FPGAlicheng/music/we.bdf
File Name with User-Entered Path : TONETABA.vhd
Used in Netlist : yes
File Type : User VHDL File
File Name with Absolute Path : D:/PLD/FPGAlicheng/music/TONETABA.vhd
File Name with User-Entered Path : NoteTabs.vhd
Used in Netlist : yes
File Type : User VHDL File
File Name with Absolute Path : D:/PLD/FPGAlicheng/music/NoteTabs.vhd
File Name with User-Entered Path : lpm_rom0.tdf
Used in Netlist : yes
File Type : User AHDL File
File Name with Absolute Path : D:/PLD/FPGAlicheng/music/lpm_rom0.tdf
File Name with User-Entered Path : altsyncram.inc
Used in Netlist : yes
File Type : Other
File Name with Absolute Path : c:/altera/quartus60/libraries/megafunctions/altsyncram.inc
File Name with User-Entered Path : altsyncram.tdf
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf
File Name with User-Entered Path : stratix_ram_block.inc
Used in Netlist : yes
File Type : Other
File Name with Absolute Path : c:/altera/quartus60/libraries/megafunctions/stratix_ram_block.inc
File Name with User-Entered Path : lpm_mux.inc
Used in Netlist : yes
File Type : Other
File Name with Absolute Path : c:/altera/quartus60/libraries/megafunctions/lpm_mux.inc
File Name with User-Entered Path : lpm_decode.inc
Used in Netlist : yes
File Type : Other
File Name with Absolute Path : c:/altera/quartus60/libraries/megafunctions/lpm_decode.inc
File Name with User-Entered Path : aglobal60.inc
Used in Netlist : yes
File Type : Other
File Name with Absolute Path : c:/altera/quartus60/libraries/megafunctions/aglobal60.inc
File Name with User-Entered Path : a_rdenreg.inc
Used in Netlist : yes
File Type : Other
File Name with Absolute Path : c:/altera/quartus60/libraries/megafunctions/a_rdenreg.inc
File Name with User-Entered Path : altrom.inc
Used in Netlist : yes
File Type : Other
File Name with Absolute Path : c:/altera/quartus60/libraries/megafunctions/altrom.inc
File Name with User-Entered Path : altram.inc
Used in Netlist : yes
File Type : Other
File Name with Absolute Path : c:/altera/quartus60/libraries/megafunctions/altram.inc
File Name with User-Entered Path : altdpram.inc
Used in Netlist : yes
File Type : Other
File Name with Absolute Path : c:/altera/quartus60/libraries/megafunctions/altdpram.inc
File Name with User-Entered Path : altqpram.inc
Used in Netlist : yes
File Type : Other
File Name with Absolute Path : c:/altera/quartus60/libraries/megafunctions/altqpram.inc
File Name with User-Entered Path : db/altsyncram_f431.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf
+--------------------------------------------------------------------------------+
+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+--------+
; Resource ; Usage ;
+---------------------------------------------+--------+
; Total logic elements ; 19 ;
; -- Combinational with no register ; 11 ;
; -- Register only ; 0 ;
; -- Combinational with a register ; 8 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 3 ;
; -- 3 input functions ; 7 ;
; -- 2 input functions ; 8 ;
; -- 1 input functions ; 1 ;
; -- 0 input functions ; 0 ;
; -- Combinational cells for routing ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 13 ;
; -- arithmetic mode ; 6 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 8 ;
; ; ;
; Total registers ; 8 ;
; Total logic cells in carry chains ; 7 ;
; I/O pins ; 8 ;
; Total memory bits ; 1024 ;
; Maximum fan-out node ; CLK8Hz ;
; Maximum fan-out ; 12 ;
; Total fan-out ; 106 ;
; Average fan-out ; 3.42 ;
+---------------------------------------------+--------+
+--------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------------------------------------+
Compilation Hierarchy Node : |we
Logic Cells : 19 (0)
LC Registers : 8
Memory Bits : 1024
M512s : 0
M4Ks : 0
M-RAMs : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
DSP 36x36 : 0
Pins : 8
Virtual Pins : 0
LUT-Only LCs : 11 (0)
Register-Only LCs : 0 (0)
LUT/Register LCs : 8 (0)
Carry Chain LCs : 7 (0)
Packed LCs : 0 (0)
Full Hierarchy Name : |we
Compilation Hierarchy Node : |NoteTabs:inst3|
Logic Cells : 11 (11)
LC Registers : 8
Memory Bits : 0
M512s : 0
M4Ks : 0
M-RAMs : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
DSP 36x36 : 0
Pins : 0
Virtual Pins : 0
LUT-Only LCs : 3 (3)
Register-Only LCs : 0 (0)
LUT/Register LCs : 8 (8)
Carry Chain LCs : 7 (7)
Packed LCs : 0 (0)
Full Hierarchy Name : |we|NoteTabs:inst3
Compilation Hierarchy Node : |TONETABA:inst2|
Logic Cells : 8 (8)
LC Registers : 0
Memory Bits : 0
M512s : 0
M4Ks : 0
M-RAMs : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
DSP 36x36 : 0
Pins : 0
Virtual Pins : 0
LUT-Only LCs : 8 (8)
Register-Only LCs : 0 (0)
LUT/Register LCs : 0 (0)
Carry Chain LCs : 0 (0)
Packed LCs : 0 (0)
Full Hierarchy Name : |we|TONETABA:inst2
Compilation Hierarchy Node : |lpm_rom0:inst|
Logic Cells : 0 (0)
LC Registers : 0
Memory Bits : 1024
M512s : 0
M4Ks : 0
M-RAMs : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
DSP 36x36 : 0
Pins : 0
Virtual Pins : 0
LUT-Only LCs : 0 (0)
Register-Only LCs : 0 (0)
LUT/Register LCs : 0 (0)
Carry Chain LCs : 0 (0)
Packed LCs : 0 (0)
Full Hierarchy Name : |we|lpm_rom0:inst
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
Logic Cells : 0 (0)
LC Registers : 0
Memory Bits : 1024
M512s : 0
M4Ks : 0
M-RAMs : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
DSP 36x36 : 0
Pins : 0
Virtual Pins : 0
LUT-Only LCs : 0 (0)
Register-Only LCs : 0 (0)
LUT/Register LCs : 0 (0)
Carry Chain LCs : 0 (0)
Packed LCs : 0 (0)
Full Hierarchy Name : |we|lpm_rom0:inst|altsyncram:altsyncram_component
Compilation Hierarchy Node : |altsyncram_f431:auto_generated|
Logic Cells : 0 (0)
LC Registers : 0
Memory Bits : 1024
M512s : 0
M4Ks : 0
M-RAMs : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
DSP 36x36 : 0
Pins : 0
Virtual Pins : 0
LUT-Only LCs : 0 (0)
Register-Only LCs : 0 (0)
LUT/Register LCs : 0 (0)
Carry Chain LCs : 0 (0)
Packed LCs : 0 (0)
Full Hierarchy Name : |we|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated
+--------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------+
Name : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ALTSYNCRAM
Type : AUTO
Mode : ROM
Port A Depth : 256
Port A Width : 4
Port B Depth : --
Port B Width : --
Size : 1024
MIF : YINYUE.mif
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+--------------------------------------------------------------------------------+
Latch Name : TONETABA:inst2|HIGH
Latch Enable Signal : TONETABA:inst2|Mux4
Free of Timing Hazards : yes
Latch Name : TONETABA:inst2|CODE[2]
Latch Enable Signal : TONETABA:inst2|Mux4
Free of Timing Hazards : yes
Latch Name : TONETABA:inst2|CODE[1]
Latch Enable Signal : TONETABA:inst2|Mux4
Free of Timing Hazards : yes
Latch Name : TONETABA:inst2|CODE[0]
Latch Enable Signal : TONETABA:inst2|Mux4
Free of Timing Hazards : yes
Latch Name : Number of user-specified and inferred latches = 4
Latch Enable Signal :
Free of Timing Hazards :
+--------------------------------------------------------------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
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