we.map.rpt

出血FPGA,用VHDL做的音乐盒

Analysis & Synthesis report for we
Tue Sep 23 20:21:51 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. User-Specified and Inferred Latches
  9. General Register Statistics
 10. Source assignments for lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated
 11. Parameter Settings for User Entity Instance: lpm_rom0:inst|altsyncram:altsyncram_component
 12. Analysis & Synthesis Equations
 13. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Sep 23 20:21:51 2008    ;
; Quartus II Version          ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name               ; we                                       ;
; Top-level Entity Name       ; we                                       ;
; Family                      ; Stratix                                  ;
; Total logic elements        ; 19                                       ;
; Total pins                  ; 8                                        ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 1,024                                    ;
; DSP block 9-bit elements    ; 0                                        ;
; Total PLLs                  ; 0                                        ;
; Total DLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                  ;
+--------------------------------------------------------------------------------+
Option        : Top-level entity name
Setting       : we
Default Value : we

Option        : Family name
Setting       : Stratix
Default Value : Stratix

Option        : Use smart compilation
Setting       : Off
Default Value : Off

Option        : Restructure Multiplexers
Setting       : Auto
Default Value : Auto

Option        : Create Debugging Nodes for IP Cores
Setting       : Off
Default Value : Off

Option        : Preserve fewer node names
Setting       : On
Default Value : On

Option        : Disable OpenCore Plus hardware evaluation
Setting       : Off
Default Value : Off

Option        : Verilog Version
Setting       : Verilog_2001
Default Value : Verilog_2001

Option        : VHDL Version
Setting       : VHDL93
Default Value : VHDL93

Option        : State Machine Processing
Setting       : Auto
Default Value : Auto

Option        : Extract Verilog State Machines
Setting       : On
Default Value : On

Option        : Extract VHDL State Machines
Setting       : On
Default Value : On

Option        : Add Pass-Through Logic to Inferred RAMs
Setting       : On
Default Value : On

Option        : DSP Block Balancing
Setting       : Auto
Default Value : Auto

Option        : Maximum DSP Block Usage
Setting       : Unlimited
Default Value : Unlimited

Option        : NOT Gate Push-Back
Setting       : On
Default Value : On

Option        : Power-Up Don't Care
Setting       : On
Default Value : On

Option        : Remove Redundant Logic Cells
Setting       : Off
Default Value : Off

Option        : Remove Duplicate Registers
Setting       : On
Default Value : On

Option        : Ignore CARRY Buffers
Setting       : Off
Default Value : Off

Option        : Ignore CASCADE Buffers
Setting       : Off
Default Value : Off

Option        : Ignore GLOBAL Buffers
Setting       : Off
Default Value : Off

Option        : Ignore ROW GLOBAL Buffers
Setting       : Off
Default Value : Off

Option        : Ignore LCELL Buffers
Setting       : Off
Default Value : Off

Option        : Ignore SOFT Buffers
Setting       : On
Default Value : On

Option        : Limit AHDL Integers to 32 Bits
Setting       : Off
Default Value : Off

Option        : Optimization Technique -- Stratix/Stratix GX
Setting       : Balanced
Default Value : Balanced

Option        : Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II
Setting       : 70
Default Value : 70

Option        : Auto Carry Chains
Setting       : On
Default Value : On

Option        : Auto Open-Drain Pins
Setting       : On
Default Value : On

Option        : Remove Duplicate Logic
Setting       : On
Default Value : On

Option        : Perform WYSIWYG Primitive Resynthesis
Setting       : Off
Default Value : Off

Option        : Perform gate-level register retiming
Setting       : Off
Default Value : Off

Option        : Allow register retiming to trade off Tsu/Tco with Fmax
Setting       : On
Default Value : On

Option        : Auto ROM Replacement
Setting       : On
Default Value : On

Option        : Auto RAM Replacement
Setting       : On
Default Value : On

Option        : Auto DSP Block Replacement
Setting       : On
Default Value : On

Option        : Auto Shift Register Replacement
Setting       : On
Default Value : On

Option        : Auto Clock Enable Replacement
Setting       : On
Default Value : On

Option        : Allow Synchronous Control Signals
Setting       : On
Default Value : On

Option        : Force Use of Synchronous Clear Signals
Setting       : Off
Default Value : Off

Option        : Auto RAM Block Balancing
Setting       : On
Default Value : On

Option        : Auto Resource Sharing
Setting       : Off
Default Value : Off

Option        : Allow Any RAM Size For Recognition
Setting       : Off
Default Value : Off

Option        : Allow Any ROM Size For Recognition
Setting       : Off
Default Value : Off

Option        : Allow Any Shift Register Size For Recognition
Setting       : Off
Default Value : Off

Option        : Maximum Number of M512 Memory Blocks
Setting       : Unlimited
Default Value : Unlimited

Option        : Maximum Number of M4K Memory Blocks
Setting       : Unlimited
Default Value : Unlimited

Option        : Maximum Number of M-RAM Memory Blocks
Setting       : Unlimited
Default Value : Unlimited

Option        : Ignore translate_off and translate_on Synthesis Directives
Setting       : Off
Default Value : Off

Option        : Show Parameter Settings Tables in Synthesis Report
Setting       : On
Default Value : On

Option        : Ignore Maximum Fan-Out Assignments
Setting       : Off
Default Value : Off

Option        : Retiming Meta-Stability Register Sequence Length
Setting       : 2
Default Value : 2

Option        : PowerPlay Power Optimization
Setting       : Normal compilation
Default Value : Normal compilation

Option        : HDL message level
Setting       : Level2
Default Value : Level2
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                         ;
+--------------------------------------------------------------------------------+
File Name with User-Entered Path : SPEAKER.vhd
Used in Netlist                  : yes
File Type                        : User VHDL File 
File Name with Absolute Path     : D:/PLD/FPGAlicheng/music/SPEAKER.vhd