key.fit.rpt

关于地铁售票的一些功能 基于自动买票的VHDL设计程序 比较经典

Fitter report for key
Thu Jun 26 11:54:13 2008
Quartus II Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Delay Chain Summary
 13. Non-Global High Fan-Out Signals
 14. Interconnect Usage Summary
 15. Fitter Device Options
 16. Fitter Messages
 17. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; Fitter Summary                                                        ;
+-----------------------+-----------------------------------------------+
; Fitter Status         ; Successful - Thu Jun 26 11:54:13 2008         ;
; Quartus II Version    ; 7.2 Build 207 03/18/2008 SP 3 SJ Full Version ;
; Revision Name         ; key                                           ;
; Top-level Entity Name ; key                                           ;
; Family                ; MAX II                                        ;
; Device                ; EPM1270T144C5                                 ;
; Timing Models         ; Final                                         ;
; Total logic elements  ; 0 / 1,270 ( 0 % )                             ;
; Total pins            ; 16 / 116 ( 14 % )                             ;
; Total virtual pins    ; 0                                             ;
; UFM blocks            ; 0 / 1 ( 0 % )                                 ;
+-----------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EPM1270T144C5                  ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Device Migration List                                              ; EPM1270T144C5                  ;                                ;
; Device I/O Standard                                                ; LVTTL                          ;                                ;
; Use smart compilation                                              ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                      ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                   ; Care                           ; Care                           ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner             ; On                             ; On                             ;
; PowerPlay Power Optimization                                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; Slow Slew Rate                                                     ; Off                            ; Off                            ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in F:/[Studio]/CPLD Competition/光盘/例程/Key/key.pin.


+-----------------------------------------------------------------+
; Fitter Resource Usage Summary                                   ;
+---------------------------------------------+-------------------+
; Resource                                    ; Usage             ;
+---------------------------------------------+-------------------+
; Total logic elements                        ; 0 / 1,270 ( 0 % ) ;
;     -- Combinational with no register       ; 0                 ;
;     -- Register only                        ; 0                 ;
;     -- Combinational with a register        ; 0                 ;
;                                             ;                   ;
; Logic element usage by number of LUT inputs ;                   ;
;     -- 4 input functions                    ; 0                 ;
;     -- 3 input functions                    ; 0                 ;